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LMC7221 Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part No. LMC7221
Description  Tiny CMOS Comparator with Rail-To-Rail Input and Open Drain Output
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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LMC7221 Datasheet(HTML) 4 Page - National Semiconductor (TI)

 
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AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for T
J = 25˚C, V
+ = 5V, V= 0V, V
CM = VO = V
+/2. Boldface limits apply at
the temperature extreme
Typ
LMC7221AI
LMC7221BI
Symbol
Parameter
Conditions
(Note 5)
Limit
Limit
Units
(Note 6)
(Note 6)
t
rise
Rise Time
f = 10 kHz, C
L = 50 pF, (Note 9)
0.3
µs
Overdrive = 10 mV, 5 k
Ω Pullup
t
fall
Fall Time
f = 10 kHz, C
L = 50 pF, (Note 9)
0.3
µs
Overdrive = 10 mV, 5 k
Ω Pullup
t
PHL
Propagation Delay
f = 10 kHz,
10 mV
10
µs
(High to Low)
C
L = 50 pF,
100 mV
4
(Note 11)
5 k
Ω Pullup
(Note 9)
V+ = 2.7V,
10 mV
10
µs
f = 10 kHz,
C
L = 50 pF,
100 mV
4
5k
Ω Pullup
(Note 9)
t
PLH
Propagation Delay
f = 10 kHz,
10 mV
6
µs
(Low to High)
C
L = 50 pF,
100 mV
4
(Note 11)
5 k
Ω Pullup
(Note 9)
V+ = 2.7V,
10 mV
7
µs
f = 10 kHz,
C
L = 50 pF,
100 mV
4
5k
Ω Pullup
(Note 9)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is in-
tended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: Human body model, 1.5 k
Ω in series with 100 pF.
Note 3: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150˚C. Output currents in excess of ±30 mA may adversely affect reliability.
Note 4: The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is
Note 5: PD = (TJ(max) −TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Note 6: Typical values represent the most likely parametric norm.
Note 7: All limits are guaranteed by testing or statistical analysis.
Note 8: Limiting input pin current is only necessary for input voltages which exceed the absolute maximum input voltage rating.
Note 9: Do not short circuit the output to V+ when V+ is greater than 12V or reliability will be adversely affected.
Note 10: CL includes the probe and test jig capacitance.
Note 11: Input offset voltage average drift is calculated by dividing the accelerated operating life VOS drift by the equivalent operational time. This represents worst
case input conditions and includes the first 30 days of drift.
Note 12: Input step voltage for propagation delay measurement is 2V.
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