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TSB43CA43A Datasheet(PDF) 74 Page - Texas Instruments |
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TSB43CA43A Datasheet(HTML) 74 Page - Texas Instruments |
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74 / 97 page  TSB43Cx43A/ TI iceLynx-Micro™ IEEE 1394a-2000 TSB43CA42 Consumer Electronics Solution TEXAS INSTRUMENTS SLLS546F – March 2004 – Revised September 2004 PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TEXAS INSTRUMENTS Copyright 2004, Texas Instruments Incorporated MARCH 12, 2004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 74 FIELD SIZE TYPE DESCRIPTION LCtrl 1 Rd/Wr Link-active status control. This bit controls the active status of the LLC as indicated during self-ID. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet. The LLC is considered active only if both the LPS input is active and the LCtrl bit is set. The LCtrl bit provides software controllable means to indicate the LLC active status in lieu of using the LPS input. The LCtrl bit is set to 1 by hardware reset and is unaffected by bus reset. Note: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of the LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active, then received packets and status information continues to be presented on the interface, and any requests indicated on the LREQ input is processed, even if the LCtrl bit is cleared to 0. C 1 Rd/Wr Contender status. This bit indicates that this node is a contender for the bus or isochronous resource manager. This bit is replicated in the c field (bit 20) of the self-ID packet. This bit is set to the state specified by the C/LKON input pin upon hardware reset and is unaffected by bus reset. Jitter 3 Rd PHY repeater jitter. This field indicates the worst-case difference between the fastest and slowest repeater data delay, expressed as (JITTER+1)*20 ns. For iceLynx-Micro this field is 0. Pwr_Class 3 Rd/Wr Node power class. This field indicates this node’s power consumption and source characteristics, and is replicated in the pwr field (bits 21–23) of the self-ID packet. This field is set to 000 default value at hardware reset and is unaffected by bus-reset. Software can program this field to change the power class. Software must perform a bus reset after setting this field. WDIE 1 Rd/Wr Watchdog interrupt enable. This bit, if set to 1, enables the port event interrupt (PEI) bit to be set whenever resume operations begin on any port. This bit also enables the C/LKON output signal to be activated whenever the LLC is inactive and any of the CTOI, CPSI, or STOI interrupt bits is set. This bit is reset to 0 by hardware reset and is unaffected by bus reset. ISBR 1 Rd/Wr Initiate short arbitrated bus-reset. This bit, if set to 1, instructs the PHY to initiate a short (1.30 µs) arbitrated bus-reset at the next opportunity. This bit is reset to 0 by bus reset. Note: Legacy IEEE Std 1394-1995 compliant PHYs may not be capable of performing short bus-resets. Therefore, initiation of a short bus-reset in a network that contains such a legacy device results in a long bus reset being performed. CTOI 1 Rd/Wr Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times out during tree-ID start, and indicates that the bus is configured in a loop. This bit is reset to 0 by hardware reset or by writing a 1 to this register bit. If the CTOI and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON output to notify the LLC to service the interrupt. Note: If the network is configured in a loop, only those nodes that are part of the loop generate a configuration time-out interrupt. All other nodes instead, time-out waiting for the tree-ID and/or self-ID process to complete and then generate a state time-out interrupt and bus reset. CPSI 1 Rd/Wr Cable power status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low indicating that cable power is too low for reliable operation. This bit is reset to 1 by a hardware reset. It is cleared by writing a 1 to this register bit. If the CPSI and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON output to notify the LLC to service the interrupt. STOI 1 Rd/Wr State time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a bus reset to occur). This bit is reset to 0 by hardware reset or by writing a 1 to this register bit. If the STOI and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON output to notify the LLC to service the interrupt. |
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