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TSB43CA42 Datasheet(PDF) 84 Page - Texas Instruments |
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TSB43CA42 Datasheet(HTML) 84 Page - Texas Instruments |
84 / 97 page TSB43Cx43A/ TI iceLynx-Micro™ IEEE 1394a-2000 TSB43CA42 Consumer Electronics Solution TEXAS INSTRUMENTS SLLS546F – March 2004 – Revised September 2004 PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TEXAS INSTRUMENTS Copyright 2004, Texas Instruments Incorporated MARCH 12, 2004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 84 Figure 46. Isochronous FIFOs 1.16.3 Asynchronous/Asynchronous Stream FIFOs These FIFOs are connected to the external and internal CPU interfaces. The transmit FIFOs are 2048 bytes each and the receive FIFOs are 2048 bytes each. Either FIFO can be configured for asynchronous stream or asynchronous packets. See Figure 47 for a block diagram of the asynchronous FIFO architecture. Figure 47. Asynchronous/ Asynchronous Stream FIFOs Note: The iceLynx-Micro has the ability to insert headers for asynchronous stream transmit. This feature must be used for asynchronous stream TX only. For any type of packet other than asynchronous stream, do not enable this feature. ISO FIFO 0 4K ISO FIFO 1 4K HSDI0 HSDI1 Packetizer Packetizer Asynchronous or Asynchrnous Stream Transmit FIFO 0 2K Asynchronous or Asynchronous Stream Transmit FIFO 1 2K External or Internal Host Packetizer/ Transmitter Packetizer/ Transmitter External or Internal Host Asynchronous or Asynchrnous Stream Receive FIFO 0 2K Asynchronous or Asynchronous Stream Receive FIFO 1 2K External or Internal Host Packetizer/ Receiver Packetizer/ Receiver External or Internal Host |
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