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TMS320F2808 Datasheet(PDF) 97 Page - Texas Instruments |
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TMS320F2808 Datasheet(HTML) 97 Page - Texas Instruments |
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97 / 123 page  www.ti.com tw(WAKE-INT) td(WAKE-STBY) td(IDLE−XCOL) Wake−up Signal X1/X2 or X1 or XCLKIN XCLKOUT STANDBY Normal Execution STANDBY Flushing Pipeline (A) (B) (C) (D) (E) (F) Device Status TMS320F2808, TMS320F2806 TMS320F2801, UCD9501 Digital Signal Processors SPRS230F – OCTOBER 2003 – REVISED SEPTEMBER 2005 Table 6-17. STANDBY Mode Switching Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Delay time, IDLE instruction ex- td(IDLE-XCOL) 32tc(SCO) 45tc(SCO) cycles ecuted to XCLKOUT low Delay time, external wake signal cycles to program execution resume(1) Without input qualifier 100tc(SCO) • Wake up from flash cycles – Flash module in active With input qualifier 100tc(SCO) + tw(WAKE-INT) state td(WAKE-STBY) Without input qualifier 1125tc(SCO) • Wake up from flash cycles – Flash module in sleep With input qualifier 1125tc(SCO) + tw(WAKE-INT) state Without input qualifier 100tc(SCO) cycles • Wake up from SARAM With input qualifier 100tc(SCO) + tw(WAKE-INT) (1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered by the wake up signal) involves additional latency. A. IDLE instruction is executed to put the device into STANDBY mode. B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being turned off. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly. C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. D. The external wake-up signal is driven active. E. After a latency period, the STANDBY mode is exited. F. Normal execution resumes. The device will respond to the interrupt (if enabled). Figure 6-12. STANDBY Entry and Exit Timing Diagram Electrical Specifications 97 |
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