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TMS320F2808 Datasheet(PDF) 91 Page - Texas Instruments |
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TMS320F2808 Datasheet(HTML) 91 Page - Texas Instruments |
91 / 123 page www.ti.com tw(RSL1) th(boot-mode)(B) VDDIO, VDD3VFL VDDA2, VDDAIO (3.3 V) XCLKIN X1/X2 XRS Boot-Mode Pins VDD, VDD1A18, VDD2A18 (1.8 V) XCLKOUT I/O Pins User-Code Dependent User-Code Dependent Boot-ROM Execution Starts Peripheral/GPIO Function Based on Boot Code GPIO Pins as Input OSCCLK/8(A) GPIO Pins as Input (State Depends on Internal PU/PD) tOSCST User-Code Dependent Address/Data/ Control (Internal) Address/Data Valid. Internal Boot-ROM Code Execution Phase User-Code Execution Phase td(EX) TMS320F2808, TMS320F2806 TMS320F2801, UCD9501 Digital Signal Processors SPRS230F – OCTOBER 2003 – REVISED SEPTEMBER 2005 A. Upon power up, SYSCLKOUT is OSCCLK/2. Since the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT = OSCCLK/8 during this phase. B. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled. Figure 6-5. Power-on Reset Electrical Specifications 91 |
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