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THC63LVD104A Datasheet(PDF) 1 Page - THine Electronics, Inc. |
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THC63LVD104A Datasheet(HTML) 1 Page - THine Electronics, Inc. |
1 / 13 page THC63LVD104A Rev.1.0 Copyright 2003 THine Electronics, Inc. All rights reserved 1 THine Electronics, Inc. THine THC63LVD104A 90MHz 30Bits COLOR LVDS Receiver General Description The THC63LVD104A receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to WXGA resolutions. The THC63LVD104A converts the LVDS data streams back into 35bits of CMOS/TTL data with rising edge or fall- ing edge clock for convenient with a variety of LCD panel controllers.At a transmit clock frequency of 90MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC,VSYNC,DE,CNTL1,CNTL2) are transmitted at an effective rate of 630Mbps per LVDS channel.Using a 90MHz clock, the data through- put is 394Mbytes per second. Features • Wide dot clock range: 8-90MHz suited for NTSC, VGA, SVGA, XGA, and WXGA • PLL requires no external components • 50% output clock duty cycle • TTL clock edge programmable • Power down mode • Low power single 3.3V CMOS design • 64pin TQFP • Backward compatible with THC63LVDF64x (18bits) / F84x(24bits) Block Diagram LVDS INPUT CMOS/TTL OUTPUT RCLK+/- (8 to90MHz) PLL RA+/- RB+/- RC+/- RD+/- RE+/- TEST PD OE R/F RA6-RA0 RB6-RB0 RC6-RC0 RD6-RD0 RE6-RE0 CLKOUT CMOS/TTL INPUT 7 7 7 7 7 |
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