SiC530

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Vishay Siliconix

S15-2523-Rev. B, 02-Nov-15

10

Document Number: 62940

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

PCB LAYOUT RECOMMENDATIONS

2. Ceramic capacitors should be placed directly between

decoupling effect.

3. Different values / packages of ceramic capacitors should

be used to cover entire decoupling spectrum e.g. 1210,

0805, 0603, 0402.

4. Smaller capacitance values, placed closer to the device’s

absorbing.



1. Connect output inductor to IC with large plane to lower

resistance.

MOSFET. Make the plane wide and short to achieve the

best thermal path.

3. If a snubber network is required, place the components

as shown above, the network can be placed at bottom.

as close as possible to the IC. It is recommended to

connect two capacitors separately.

instantaneous driver current for low side MOSFET during

switching cycle.

a large plane to reduce parasitic inductance.



Step 4: BOOT Resistor and Capacitor Placement

1. The components need to be placed as close as possible

to IC, directly between PHASE (pin 5) and BOOT (pin 4).

2. To reduce parasitic inductance, chip size 0402 can be

used.

Snubber

Cboot

Rboot