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SCC2681AC1A44 Datasheet(PDF) 21 Page - NXP Semiconductors

Part # SCC2681AC1A44
Description  Dual asynchronous receiver/transmitter (DUART)
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SCC2681AC1A44 Datasheet(HTML) 21 Page - NXP Semiconductors

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Product data
SCC2681
Dual asynchronous receiver/transmitter (DUART)
2004 Apr 06
21
Table 5.
Baud Rates Extended
Normal BRG
BRG Extended Rates
CSR[7:4]
ACR[7] = 0
ACR[7] = 1
ACR[7] = 0
ACR[7] = 1
0000
50
75
4,800
7,200
0001
110
110
880
880
0010
134.5
134.5
1,076
1,076
0011
200
150
19.2 k
14.4 k
0100
300
300
28.8 k
28.8 k
0101
600
600
57.6 k
57.6 k
0110
1,200
1,200
115.2 k
115.2 k
0111
1,050
2,000
1,050
2,000
1000
2,400
2,400
57.6 k
57.6 k
1001
4,800
4,800
4,800
4,800
1010
7,200
1,800
57.6 k
14.4 k
1011
9,600
9,600
9,600
9,600
1100
38.4 k
19.2 k
38.4 k
19.2 k
1101
Timer
Timer
Timer
Timer
1110
I/O2 – 16
×
I/O2 – 16
×
I/O2 – 16
×
I/O2 – 16
×
1111
I/O2 – 1
×
I/O2 – 1
×
I/O2 – 1
×
I/O2 – 1
×
NOTE: Each read on address H‘2’ will toggle the baud rate test mode. When in the BRG test mode, the baud rates change as shown to the left.
This change affects all receivers and transmitters on the DUART. See
“Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68692 and SCC2698B” in application notes elsewhere in this publication.
The test mode at address H‘A’ changes all transmitters and receivers to the 1
× mode and connects the output ports to some internal nodes.
Receiver Reset in the Normal Mode (Receiver Enabled)
Reset can be accomplished easily by issuing a receiver software or hardware reset followed by a receiver enable. All receiver data,
status and programming will be preserved and available before reset. The reset will NOT affect the programming.
Receiver Reset in the Wake-Up Mode (MR1[4:3] = 11)
Reset can also be accomplished easily by first exiting the wake-up mode (MR1[4:3] = 00 or 01 or 10), then issuing a receiver software or
hardware reset followed by a wake-up re-entry (MR1[4:3] = 11). All receiver data, status and programming will be preserved and
available before reset. The reset will NOT affect other programming.
The reason for this is the receiver is partially enabled when the parity bits are at ‘11’. Thus the receiver disable and reset is bypassed by
the partial enabling of the receiver.
SD00097


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