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AD7477AAKSZ-REEL73 Datasheet(PDF) 6 Page - Analog Devices |
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AD7477AAKSZ-REEL73 Datasheet(HTML) 6 Page - Analog Devices |
6 / 24 page REV. C –6– AD7476A/AD7477A/AD7478A TIMING SPECIFICATIONS1 (V DD = 2.35 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted.) Limit at TMIN, TMAX Parameter AD7476A/AD7477A/AD7478A Unit Description fSCLK 2 10 kHz min 3 A, B Grades 20 kHz min 3 Y Grade 20 MHz max tCONVERT 16 tSCLK AD7476A 14 tSCLK AD7477A 12 tSCLK AD7478A tQUIET 50 ns min Minimum Quiet Time Required between Bus Relinquish and Start of Next Conversion t1 10 ns min Minimum CS Pulse Width t2 10 ns min CS to SCLK Setup Time t3 4 22 ns max Delay from CS until SDATA Three-State Disabled t4 4 40 ns max Data Access Time after SCLK Falling Edge t5 0.4 tSCLK ns min SCLK Low Pulse Width t6 0.4 tSCLK ns min SCLK High Pulse Width t7 5 SCLK to Data Valid Hold Time 10 ns min VDD ≤ 3.3 V 9.5 ns min 3.3 V < VDD ≤ 3.6 V 7 ns min VDD > 3.6 V t8 6 36 ns max SCLK Falling Edge to SDATA High Impedance See Note 7 ns min SCLK Falling Edge to SDATA High Impedance tPOWER-UP 8 1 µs max Power-Up Time from Full Power-Down NOTES 1Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. 2Mark/space ratio for the SCLK input is 40/60 to 60/40. 3Minimum f SCLK at which specifications are guaranteed. 4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 1.8 V when V DD = 2.35 V and 0.8 V or 2.0 V for VDD > 2.35 V. 5Measured with 50 pF load capacitor. 6t 8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number i s then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7t 7 values also apply to t8 minimum values. 8See Power-Up Time section. Specifications subject to change without notice. TO OUTPUT PIN CL 50pF 200 A IOH 200 A IOL 1.6V Figure 1. Load Circuit for Digital Output Timing Specifications |
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