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ADT7516 Datasheet(PDF) 38 Page - Analog Devices

Part No. ADT7516
Description  SPI/I2C Compatible, Temperature Sensor, Four Channel ADC and Quad Voltage Output DAC
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADT7516 Datasheet(HTML) 38 Page - Analog Devices

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ADT7516/ADT7517/ADT7519
Rev. A | Page 38 of 44
ADT7516/
ADT7517/
ADT7519
CS
SDA
SCL
ADD
VDD
VDD
I2C ADDRESS = 1001 000
10k
10k
Figure 57. Typical I2C Interface Connection
ADT7516/
ADT7517/
ADT7519
SCLK
DOUT
CS
VDD
LOCK AND
SELECT SPI
SPI FRAMING
EDGE
820
820
820
DIN
Figure 58. Typical SPI Interface Connection
A
B
CS
(START HIGH)
SPI LOCKED ON
THIRD RISING EDGE
C
SPI FRAMING
EDGE
A
B
CS
(START LOW)
SPI LOCKED ON
THIRD RISING EDGE
C
SPI FRAMING
EDGE
Figure 59. Serial Interface—Selecting and Locking SPI Protocol
I2C Serial Interface
Like all I2C compatible devices, the ADT7516/ADT7517/
ADT7519 have a 7-bit serial address. The four MSBs of this
address for the ADT7516/ADT7517/ADT7519 are set to 1001.
The three LSBs are set by Pin 11, ADD. The ADD pin can be
configured three ways to give three different address options:
low, floating, and high. Setting the ADD pin low gives a serial
bus address of 1001 000, leaving it floating gives the address
1001 010, and setting it high gives the address 1001 011. The
recommended pull-up resistor value is 10 kΩ.
There is an enable/disable bit for the SMBus timeout. When this
is enabled, the SMBus will time out after 25 ms of no activity. To
enable it, set Bit 6 of the Control Configuration 2 register. The
power-on default is with the SMBus timeout disabled.
The ADT7516/ADT7517/ADT7519 support SMBus packet
error checking (PEC), but its use is optional. It is triggered by
supplying the extra clocks for the PEC byte. The PEC is
calculated using CRC-8. The frame clock sequence (FCS)
conforms to CRC-8 by the polynominal
()
1
1
2
8
+
+
+
=
x
x
x
x
C
Consult the SMBus specification (www.smbus.org) for more
information.
The serial bus protocol operates as follows:
1.
The master initiates a data transfer by establishing a start
condition, defined as a high to low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
start condition and shift in the next eight bits, consisting of
a 7-bit address (MSB first) plus a R/W bit, which
determines the direction of the data transfer, i.e., whether
data will be written to or read from the slave device.
The peripheral whose address corresponds to the
transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse, known
as the Acknowledge Bit. All other devices on the bus now
remain idle while the selected device waits for data to be
read from or written to it. If the R/W bit is 0 the master will
write to the slave device. If the R/W bit is 1, the master will
read from the slave device.
2.
Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the receiver of data. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, because a low to high tran-
sition when the clock is high may be interpreted as a stop
signal.
3.
When all data bytes have been read or written, stop
conditions are established. In write mode, the master will
pull the data line high during the 10th clock pulse to assert
a stop condition. In read mode, the master device will pull
the data line high during the low period before the ninth
clock pulse. This is known as No Acknowledge. The master
will then take the data line low during the low period
before the 10th clock pulse, and then high during the 10th
clock pulse to assert a stop condition.


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