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ADT7516 Datasheet(PDF) 5 Page - Analog Devices

Part No. ADT7516
Description  SPI/I2C Compatible, Temperature Sensor, Four Channel ADC and Quad Voltage Output DAC
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADT7516 Datasheet(HTML) 5 Page - Analog Devices

 
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ADT7516/ADT7517/ADT7519
Rev. A | Page 5 of 44
Parameter1
Min
Typ
Max
Unit
Conditions/Comments
ON-CHIP REFERENCE
Reference Voltage
4
2.28
V
Temperature Coefficient4
80
ppm/°C
OUTPUT CHARACTERISTICS
4
Output Voltage 6
0.001
VDD − 0.1
V
This is a measure of the minimum and maximum
drive capability of the output amplifier.
DC Output Impedance
0.5
Short Circuit Current
25
mA
VDD = 5 V.
16
mA
VDD = 3 V.
Power-Up Time
2.5
µs
Coming out of power-down mode. VDD = 5 V.
5
µs
Coming out of power-down mode. VDD = 3.3 V.
DIGITAL INPUTS
4
Input Current
±1
µA
VIN = 0 V to VDD.
VIL, Input Low Voltage
0.8
V
VIH, Input High Voltage
1.89
V
Pin Capacitance
3
10
pF
All digital inputs.
SCL, SDA Glitch Rejection
50
ns
Input filtering suppresses noise spikes of less
than 50 ns.
LDAC Pulse Width
20
ns
Edge triggered input.
DIGITAL OUTPUT
Digital High Voltage, VOH
2.4
V
ISOURCE = ISINK = 200 µA.
Output Low Voltage, VOL
0.4
V
IOL = 3 mA.
Output High Current, IOH
1
mA
VOH = 5 V.
Output Capacitance, COUT
50
pF
INT/INT Output Saturation Voltage
0.8
V
IOUT = 4 mA.
I2C TIMING CHARACTERISTICS 7, 8
Serial Clock Period, t1
2.5
µs
Fast Mode I2C. See Figure 2.
Data In Setup Time to SCL High, t2
50
ns
Data Out Stable after SCL Low, t3
0
ns
See Figure 2.
SDA Low Setup Time to SCL
Low (Start Condition), t4
50
ns
See Figure 2.
SDA High Hold Time after SCL
High (Stop Condition), t5
50
ns
See Figure 2.
SDA and SCL Fall Time, t6
90
ns
See Figure 2.
SPI TIMING CHARACTERISTICS
4
, 9
CS to SCLK Setup Time, t1
0
ns
See Figure 3.
SCLK High Pulse Width, t2
50
ns
See Figure 3.
SCLK Low Pulse Width, t3
50
ns
See Figure 3.
Data Access Time after SCLK
Falling Edge, t4, 10
35
ns
Data Setup Time Prior to SCLK
Rising Edge, t5
20
ns
See Figure 3.
Data Hold Time after SCLK Rising
Edge, t6
0
ns
See Figure 3.
CS to SCLK Hold Time, t7
0
µs
See Figure 3.
CS to DOUT High Impedance, t8
40
ns
See Figure 3.


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