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LMC1983 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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LMC1983 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 14 page Pin Description CLK (1) The INTERMETAL (IM) Bus clock is applied to the CLOCK pin. This input accepts a TTL or CMOS level signal. The input is used to clock the DATA signal. A data bit must be valid on the rising clock edge. DIGITAL INPUT 1 & 2 (2, 3) Internally tied high to V + through a 30 k Ω pull-up resistor, these inputs al- low a peripheral device to place any single-bit, active low digital information onto the IM Bus. It is then sent out to the controlling device through the DATA pin. Examples of such informa- tion could include indication of the presence of a Second Audio Program (SAP) or an FM stereo carrier. INPUTS 1,2&3 (4, 25; 5, 24; 6, 23) These are the LMC1983’s three stereo input pairs. SELECT OUT (7, 22) The selected INPUT signal is available at this output. This feature allows ex- ternal signal processors such as noise reduction or graphic equalizers to be used. This output can typically sink 1 mA. These pins should be capaci- tively coupled to pins 8 and 21, re- spectively, if no external processor is used. SELECT IN (8, 21) These are the inputs that an external signal processor uses to return a sig- nal to the LMC1983. These pins should be capacitively coupled to pins 7 and 22, respectively, if no external processor is used. TONE IN (9, 20) These are the inputs to the tone con- trol amplifier. See the Application Infor- mation section titled “Tone Control Re- sponse”. TONE OUT (10, 19) Tone control amplifier output. See the Application Information section titled “Tone Control Response”. OP AMP OUT (11, 18) These outputs are used with external tone control capacitors. Internally, this output is applied to the volume attenu- ators. LOUDNESS (12, 17) The output signal on these pins is a voltage taken from the volume attenu- ator’s −40 dB tap point. An external R–C network is connected to these pins. MAIN OUTPUT (13, 16) The output signal from these pins drives a stereo power amplifier. The output can typically sink 1 mA. BYPASS (14) A 10 µF capacitor is connected be- tween this pin and ground to provide an AC ground for the internal half-supply voltage reference. GROUND (15) This pin is connected to analog ground. V+ (26) This is the power supply connection. The LMC1983 is operational with sup- ply voltages from 6V to 12V. This pin should be bypassed to ground through a 1.0 µF capacitor. ID (27) This is the IDENTITY digital input that, when low, signals the LMC1983 to re- ceive, from a controlling device, a de- vice address (40 H–47H), present on the DATA line. DATA (28) This is the serial data input for commu- nications sent by a controller. The con- troller must have open drain outputs used with external pull-up resistors. The data rate has a maximum fre- quency of 1 MHz. The LMC1983 re- quires 16 bits of data to control or change a function: the first 8 bits select the LMC1983 and one of eight func- tions. The final eight bits set the func- tion to a desired value. The data must be valid on the rising edge of the CLOCK input signal. General Information The LMC1983 is a CMOS/bipolar building block intended for high fidelity audio signal processing. It is designed for line level inputs signals (300 mV − 2V) and has a maximum gain of −0.5 dB. While the LMC1983 is manufactured with CMOS processing, NPN transistors are used to build low noise op amps. The combination of CMOS switches, bipolar op amps, and poly-silicon resistors make it possible to achieve an or- der of magnitude quality improvement over other bipolar cir- cuits that use analog multipliers to accomplish gain adjust- ment. Internal circuits set the volume to minimum, tone controls to flat, the mute to on, and all other functions off when power is first applied. Individual left and right volume controls are software programmed to achieve the stereo bal- ance function. Figure 1 shows the connection diagram of a typical LMC1983 application. The LMC1983 has internal decoding logic that allows a mi- croprocessor (µP) or microcontroller (µC) to communicate di- rectly to the audio control circuitry through an INTERMETAL (IM) Bus interface. This three-wire interface consists of a bi-directional DATA line, a Clock (CLK) input line, and an Identity (ID) line. Address and function selection data (8 bits) are serially shifted from the controller to the LMC1983. This is followed by 8 bits of function value data. Data present in the internal shift register is latched and the instruction is executed. www.national.com 6 |
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