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TPS61178 Datasheet(PDF) 3 Page - Texas Instruments |
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TPS61178 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 35 page  FREQ/SYNC AGND ILIMIT COMP FB BST VIN EN VCC DISDRV 9 10 12 6 7 8 13 11 5 4 2 1 3 3 TPS61178, TPS611781 www.ti.com SLVSDA7 – FEBRUARY 2017 Product Folder Links: TPS61178 TPS611781 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 5 Device Comparison Table Part Number Operation Mode at Light Load TPS61178 Auto PFM TPS611781 Forced PWM 6 Pin Configuration and Functions (RNW) (13-Pin QFN) Top View Pin Functions PIN I/O DESCRIPTION NAME NUMBER FREQ / SYNC 1 I The switching frequency is programmed by a resistor between this pin and the AGND. The internal oscillator can be synchronized by an external clock connecting into this pin. This pin can not be float in application. AGND 2 - Analog signal ground of the IC. Connect the AGND to PGND via a single point on the printed circuit board. ILIMIT 3 I Programming the switching peak current limit by a resistor between this pin and AGND. COMP 4 O Output of the internal error amplifier. The loop compensation network should be connected between this pin and AGND. FB 5 I Output voltage feedback, a resistor divider connecting to this pin sets the output voltage. PGND 6 PWR Power ground SW 7 PWR The switching node pin of the converter. It is connected to the drain of the internal low-side power FET and the source of the internal high-side power FET. VOUT 8 PWR Boost converter output DISDRV 9 O A gate drive output for the external disconnect FET. Connect the DISDRV pin to the gate of the external FET. Leave it floating if not using the load disconnect function. VCC 10 O Output of the internal regulator. A ceramic capacitor of more than 1.0 µF is required between this pin and ground EN 11 I Enable logic input. Logic high level enables the device and low level shutdown the device. VIN 12 I IC power supply input. BST 13 O Power supply for high-side FET gate driver. A capacitor must be connected between this pin and the SW pin |
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