Electronic Components Datasheet Search |
|
ADC128S102MDR Datasheet(PDF) 10 Page - Texas Instruments |
|
|
ADC128S102MDR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 32 page tCSH SCLK CS tCSS CS tCONVERT tACQ tCH tCL tDACC tEN tDH tDS FOUR ZEROS DB10 DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC DB11 DB9 DB8 DB1 16 8 7 6 5 4 3 2 1 DB0 DIN DOUT SCLK CS tDIS tDHLD 8 9 10 11 12 13 14 15 16 Track Hold Power Up ADD2 ADD1 ADD0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DIN DOUT SCLK CS Control register N 1 2 3 4 5 6 7 1 2 3 4 5 6 7 ADD2 ADD1 ADD0 8 DB11 DB10 DB9 Power Down Power Up Track Hold FOUR ZEROS FOUR ZEROS DB1 DB0 Control register N + 1 Data N ± 1 Data N 10 ADC128S102QML-SP SNAS411O – AUGUST 2008 – REVISED AUGUST 2016 www.ti.com Product Folder Links: ADC128S102QML-SP Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Figure 1. ADC128S102 Operational Timing Diagram Figure 2. ADC128S102 Serial Timing Diagram Figure 3. SCLK and CS Timing Parameters |
Similar Part No. - ADC128S102MDR |
|
Similar Description - ADC128S102MDR |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |