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DRV3220QPHPRQ1 Datasheet(PDF) 11 Page - Texas Instruments |
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DRV3220QPHPRQ1 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 31 page  NCS SCLK SDI SDO tsucs thigh tsusi tlow td2 td1 td1 ttri tsusi tsucs thlcs thcs 11 DRV3220-Q1 www.ti.com SLVSDM3 – FEBRUARY 2017 Product Folder Links: DRV3220-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) The maximum SPI clock tolerance is ±10%. (2) Ensured by characterization. (3) Ensured by characterization. 6.6 Serial Peripheral Interface Timing Requirements POS 13 MIN NOM MAX UNIT 13.1 ƒSPI SPI clock (SCLK) frequency 4(1) MHz 13.2 tSPI SPI clock period(2) 250 ns 13.3 thigh High time: SCLK logic high duration(2) 90 ns 13.4 tlow Low time: SCLK logic low duration(2) 90 ns 13.5 tsucs Setup time NCS: time between falling edge of NCS and rising edge of SCLK (2) tSPI / 2 ns 13.6 td1 Delay time: time delay from falling edge of NCS to data valid at SDO(3) 60 ns 13.7 tsusi Setup time at SDI: setup time of SDI before the rising edge of SCLK (2) 30 ns 13.8 td2 Delay time: time delay from falling edge of SCLK to data valid at SDO (3) 0 60 ns 13.9 thcs Hold time: time between the falling edge of SCLK and rising edge of NCS (2) 45 ns 13.10 thlcs SPI transfer inactive time (time between two transfers)(2) 250 ns 13.11 ttri Tri-state delay time: time between rising edge of NCS and SDO in tri-state(2) 30 ns Figure 1. SPI Timing Parameters |
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