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LM5070MTC-80 Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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LM5070MTC-80 Datasheet(HTML) 11 Page - National Semiconductor (TI) |
11 / 17 page TABLE 1. Operating Modes With Respect to Input Voltage Input Voltage V IN wrt VEE Mode of Operation 1.8V to 10.0V Detection (Signature) 12.5V to 20.5V Classification 23.0V to UVLO Rising Vth Awaiting Full Power 75V to UVLO Falling Vth Normal Powered Operation An external signature resistor is connected to V EE when VIN exceeds 1.8V, initiating detection mode. During detection mode, quiescent current drawn by the LM5070 is less than 10uA. Between 10.0V and 12.5V, the device enters classifi- cation mode and the signature resistor is disabled. The nominal range for classification mode is 11.5V to 21.5V. The classification current is turned off once the classification range voltage is exceeded, to reduce power dissipation. Between 21.5V and UVLO release, the device is in a standby state, awaiting the input voltage to reach the opera- tional range to complete the power up sequence. Once the V IN voltage increases above the upper UVLO threshold volt- age, the internal power MOSFET is enabled to deliver a constant current to charge the input capacitor of the dc-dc converter. When the MOSFET Vds voltage falls below 1.5V, the internal Power Good signal enables the SMPS controller. The LM5070 is specified to operate with an input voltage as high as 75V. The SMPS controller and internal MOSFET are disabled when V IN falls to the lower UVLO threshold. Detection Signature To detect a potential powered device candidate, the PSE will apply a voltage from 2.8V to 10V across the input terminals of the PD. The voltage can be of either polarity so a diode barrel network is required on both lines to ensure this capa- bility. The PSE will take two measurements, separated by at least 1V and 2ms of time. The voltage ramp between mea- surement points will not exceed 0.1V/us. The delta voltage / delta current calculation is then performed; if the detected impedance is above 23.75k Ω and below 26.25kΩ, the PSE will consider a PD to be present. If the impedance is less than 15k Ω or greater than 33kΩ a PD will be considered not present and will not receive power. Impedances between these values may or may not indicate the presence of a valid PD. The LM5070 will enable the signature resistor at a controller input voltage of 1.5V to take into account the diode voltage drops. The PSE will tolerate no more than 1.9V of offset voltage (caused by the external diodes) or more than 10uA of offset current (bias current). The input capacitance must be greater than 0.05uF and less than 0.12uF. To in- crease efficiency, the signature resistor is disabled by the LM5070 controller once the input voltage is above the de- tection range (> 11V). Classification To classify the PD, the PSE will present a voltage between 14.5V and 20.5V to the PD. The LM5070 enables classifica- tion mode at a nominal input voltage of 11.5V. An internal 1.5V linear regulator and an external resistor connected to the RCLASS pin provide classification programming current. Table 2 shows the external classification resistor required for a particular class. The classification current flows through the IC into the clas- sification resistor. The suggested resistor values take into account the bias current flowing into the IC. A different desired RCLASS can be calculated by dividing 1.5V by the desired classification current. Per the IEEE 802.3af specification, classification is optional, and the PSE will default to class 0 if a valid classification current is not detected. If PD classification is not desired (i.e., Class 0), simply leave the RCLASS pin open. The classification time period may not last longer then 75ms as per IEEE 802.3af. The LM5070 will remain in classification mode until V IN is greater than 22V. TABLE 2. Classification Levels and Required External Resistors Class PMIN PMAX ICLASS (MIN) ICLASS (MAX) RCLASS 0 0.44W 12.95W 0mA 4mA Open 1 0.44W 3.84W 9mA 12mA 150 Ω 2 3.84W 6.49W 17mA 20mA 82.5 Ω 3 6.49W 12.95W 26mA 30mA 53.6 Ω 4 Reserved Reserved 36mA 44mA 38.3 Ω Undervoltage Lockout (UVLO) The IEEE 802.3af specification states that the PSE will supply power to the PD within 400ms after completion of detection. The LM5070 contains a programmable line Under Voltage Lock Out (UVLO) circuit. The first resistor should be connected between the V IN to UVLO pins; the bottom resis- tor in the divider should be connected between the UVLO and UVLORTN pins. The bottom resistor should not be tied to V EE because any current from VIN to VEE will cause the system to violate the 10uA maximum offset current specifi- cation during detection mode. The divider must be designed such that the voltage at the UVLO pin equals 2.0V when V IN reaches the desired mini- mum operating level. If the UVLO threshold is not met, the interface control and SMPS control will remain in standby. UVLO hysteresis is accomplished with an internal 10uA current source that is switched on and off into the impedance of the UVLO set point divider. When the UVLO threshold is exceeded, the current source is activated to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 2.00V threshold, the current source is turned off, causing the voltage at the UVLO pin to fall. The LM5070 UVLO thresholds cannot be programmed lower than 23V, otherwise the device would operate in classification mode with both the classification current source and the SMPS enabled. The combined power dissipation of these two func- tions could exceed the maximum power dissipation of the package. There are many additional uses for the UVLO pin. The UVLO function can also be used to implement a remote enable / disable function. Pulling the UVLO pin down below the UVLO threshold disables the interface and SMPS controller. Power Supply Operation / Current Limit Programming Once the UVLO threshold has been satisfied, the interface controller of the LM5070 will charge up the SMPS input capacitor through the internal power MOSFET. This load www.national.com 11 |
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