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LM9627 Datasheet(PDF) 27 Page - National Semiconductor (TI) |
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LM9627 Datasheet(HTML) 27 Page - National Semiconductor (TI) |
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27 / 37 page  Confidential 27 www.national.com Register Set (continued) Register Name Snapshot Mode Configuration Register 0 Address 09 Hex Mnemonic SNAPMODE0 Type Read/Write Reset Value 00 Hex Register Name Snapshot Mode Configuration Register 1 Address 0A Hex Mnemonic SNAPMODE1 Type Read/Write Reset Value 00 Hex. Bit Bit Symbol Description 7.6 SsFrames Program to set the number of frames required before readout during a snapshot with no external shutter, (see Figure 18). By default these two bits are set to 00 resulting in one frame before readout: 5 ShutterEn Assert to indicate that an external shutter will be used during snap- shot mode. Clear (the default) to indicate that snapshot mode will be carried out without the aid of an external shutter. 4 ExtSynPol Assert to set the active level of the extsync signal to 0. Clear (the default) to set the active level of the extsync signal to 1. 3 Reserved 2 SnapshotMod Assert to set the snapshot pin to level mode. In level mode the sen- sor will continually run snapshot sequences as long as the snap- shot pin is held to the active level. Clear (the default) to set the snap- shot signal to pulse mode. In pulse mode the sensor will only carry out one snapshot sequence per pulse applied to the snapshot pin. 1 SnapShotPol Assert to set the snapshot pin to be active on the positive edge. Clear (the default) to set the snap- shot pin to be active on the nega- tive edge. 0 IrqPol Assert to set the active level of the irq signal to 0, Clear (the default) to set the active level of the irq signal to 1. 0 one frame 01 two frames 10 three frames 11 four frames Bit Bit Symbol Description 7 SnapIntEn Assert to enable the snapshot interrupt generator. Clear (the default) to disable the interrupt generator. 6 SsTrigFlag (Read Only Bit) Snapshot trigger interrupt flag. A logic 1 in this bit indicates that the generated interrupt on the irq pin is due to a snapshot trig- ger. This bit is cleared when read. 5 SsRdFlag (Read Only Bit) Snapshot read done interrupt flag. A logic 1 in this bit indicates that the generated interrupt on the irq pin is due to the comple- tion of a snapshot readout sequence. This bit is cleared when read. 4 SsEngage Assert to allow a CPU controlled snapshot sequence. In this mode the snapshot trigger will only generate an interrupt to the CPU and the CPU must manu- ally start the snapshot sequence by asserting the FTriggerEn bit of this register. Clear (the default) engage an automatic snapshot sequence. In auto mode the snapshot sequence is started as soon as a snapshot trigger is asserted. 3 FtSync (Read Only Bit) The internal synchronisation signal. A logic 1 on this bit indi- cates a synchronization event is required. This bit is functionally equivalent to the external extsync pin. 2 FtBusy (Read Only Bit) The Frame Trigger Busy bit. A logic 1 on this bit indicates that the sensor is busy reading out pixel data as shown in Figure 18. 1 FTriggerNow Assert to start a snapshot sequence. The frame trigger now is functionally equivalent to the external snapshot pin. The default is 0. 0 FTriggerEn Assert to enable a snapshot sequence (see the SsEngage bit of this register). The default is 0. |
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