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KM416S1120D Datasheet(PDF) 6 Page - List of Unclassifed Manufacturers

Part No. KM416S1120D
Description  512K x 16bit x 2 Banks Synchronous DRAM LVTTL
Download  43 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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KM416S1120D
CMOS SDRAM
- 6 -
Rev. 1.4 (Jun. 1999)
1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.
2. Measured with outputs open. Addresses are changed only one time during tcc(min).
3. Refresh period is 32ms. Addresses are changed only one time during tcc(min).
4. KM416S1120DT-G**
5. KM416S1120DT-F**
Note :
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70
°C)
Parameter
Symbol
Test Condition
CAS
Latency
Version
Unit Note
-C
-6
-7
-8
-10
Operating Current
(One Bank Active)
ICC1
Burst Length =1
tRC
≥tRC(min)
Io = 0 mA
3
120
115
105
95
85
mA
2
2
-
-
110
95
80
Precharge Standby Cur-
rent in power-down mode
ICC2P
CKE
≤VIL(max), tCC = 15ns
2
mA
ICC2PS
CKE & CLK
≤VIL(max), tCC = ∞
2
Precharge Standby Current
in non power-down mode
ICC2N
CKE
≥VIH(min), CS≥VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
15
mA
ICC2NS
CKE
≥VIH(min), CLK≤VIL(max), tCC = ∞
Input signals are stable
5
Active Standby Current
in power-down mode
ICC3P
CKE
≤VIL(max), tCC = 15ns
3
mA
ICC3PS
CKE & CLK
≤VIL(max), tCC = ∞
3
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3N
CKE
≥VIH(min), CS≥VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
25
mA
ICC3NS
CKE
≥VIH(min), CLK≤VIL(max), tCC = ∞
Input signals are stable
15
mA
Operating Current
(Burst Mode)
ICC4
Io = 0 mA
Page Burst 2Banks Activated
tCCD = 2CLKs
3
155
150
140
130
115
mA
2
2
-
-
125
115
100
Refresh Current
ICC5
tRC
≥tRC(min)
3
105
100
90
90
80
mA
3
2
-
-
100
90
80
Self Refresh Current
ICC6
CKE
≤0.2V
1
mA
4
250
uA
5


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