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KM416S1120D Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

Part No. KM416S1120D
Description  512K x 16bit x 2 Banks Synchronous DRAM LVTTL
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KM416S1120D Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers

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KM416S1120D
CMOS SDRAM
- 3 -
Rev. 1.4 (Jun. 1999)
The KM416S1120D is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with SAMSUNG
′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
• 3.3V power supply
• LVTTL compatible with multiplexed address
• Dual banks operation
• MRS cycle with address key programs
-. CAS Latency ( 2 & 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
• Burst Read Single-bit Write operation
• DQM for masking
• Auto & self refresh
• 15.6us refresh duty cycle (2K/32ms)
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
512K x 16Bit x 2 Banks Synchronous DRAM
ORDERING INFORMATION
Part NO.
MAX Freq.
Interface Package
KM416S1120DT-G/FC
183MHz
LVTTL
50
TSOP(II)
KM416S1120DT-G/F6
166MHz
KM416S1120DT-G/F7
143MHz
KM416S1120DT-G/F8
125MHz
KM416S1120DT-G/F10
100MHz
Samsung Electronics reserves the right to
change products or specification without
notice.
*
Bank Select
Data Input Register
512K x 16
512K x 16
Column Decoder
Latency & Burst Length
Programming Register
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
Timing Register


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