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MC145507 Datasheet(PDF) 7 Page - Motorola, Inc |
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MC145507 Datasheet(HTML) 7 Page - Motorola, Inc |
7 / 24 page MC145506 •MC145507•MC145508 MOTOROLA 7 DEVICE DESCRIPTIONS A codec–filter is a device which is used for digitizing and reconstructing the human voice. These devices were devel- oped primarily for the telephone network to facilitate voice switching and transmission. Once the voice is digitized, it may be switched by digital switching methods or transmitted long distance (T1, microwave, satellites, etc.) without degra- dation. The name codec is an acronym from “coder” for the A/D used to digitize voice, and “decoder” for the D/A used for reconstructing voice. A codec is a single device that does both the A/D and D/A conversions. To digitize intelligible voice requires a signal to distortion of about 30 dB for a dynamic range of about 40 dB. This may be accomplished with a linear 13–bit A/D and D/A, but will far ex- ceed the required signal to distortion at amplitudes greater than 40 dB below the peak amplitude. This excess perform- ance is at the expense of data per sample. Two methods of data reduction are implemented by compressing the 13–bit linear scheme to companded 8–bit schemes. These com- panding schemes follow a segmented or “piecewise–linear” curve formatted as a sign bit, 3 chord bits, and 4 step bits. For a given chord, all 16 of the steps have the same voltage weighting. As the voltage of the analog input increases, the 4 step bits increment and carry to the 3 chord bits which incre- ment. With the chord bits incremented, the step bits double their voltage weighting. This results in an effective resolution of 6 bits (sign + chord + 4 step bits) across a 42 dB dynamic range (7 chords above 0, by 6 dB per chord). There are two companding schemes used; Mu–255 Law specifically in North America, and A–Law specifically in Europe. These companding schemes are accepted world wide. The tables show the linear quantization levels to PCM words for the two companding schemes. In a sampling environment, Nyquist theory says that to properly sample a continuous signal, it must be sampled at a frequency higher than twice the signal’s highest frequency component. Voice contains spectral energy above 3 kHz, but its absence is not detrimental to intelligibility. To reduce the digital data rate, which is proportional to the sampling rate, a sample rate of 8 kHz was adopted, consistent with a band- width of 3 kHz. This sampling requires a low–pass filter to limit the high frequency energy above 3 kHz from distorting the inband signal. The telephone line is also subject to 50/60 Hz power line coupling which must be attenuated from the signal by a high–pass filter before the A/D converter. The D/A process reconstructs a staircase version of the desired inband signal which has spectral images of the in- band signal modulated about the sample frequency and its harmonics. These spectral images are called aliasing compo- nents which need to be attenuated to obtain the desired sig- nal. The low–pass filter used to attenuate these aliasing components is typically called a reconstruction or smoothing filter. The MC145500 series PCM codec–filters have the codec, both presampling and reconstruction filters, a precision volt- age reference on chip, and require no external components. There are three distinct versions of the Motorola MC145500 series with HCMOS compatible outputs. MC145506 The MC145506 PCM codec–filter is the full–featured 22–pin device. It is intended for use in applications requiring maximum flexibility. The MC145506 contains all the features of the MC145507 and MC145508. The MC145506 is in- tended for bit interleaved or byte interleaved applications with data clock frequencies which are nonstandard or time vary- ing. One of the five standard frequencies (listed below) is ap- plied to the CCI input, and the data clock inputs can be any frequency between 64 kHz and 4.096 MHz. The Vref pin allows for use of an external shared reference or selection of the internal reference. The RxG pin accommodates gain ad- justments for the inverted analog output. All three pins of the input gainsetting operational amplifier are present which pro- vide maximum flexibility for the analog interface. MC145507 The MC145507 PCM mono–circuit is intended for standard byte interleaved synchronous or asynchronous applications. TDC can be one of five discrete frequencies. These are 128 kHz (40% to 60% duty cycle), 1.536 MHz, 1.544 MHz, 2.048 MHz, or 2.56 MHz. (For other data clock frequencies, see MC145506 or MC145508.) The internal reference is set for 3.15 V peak full scale, and the full scale input level at TxI and output level at RxO is 6.3 Vp–p. This is the 3 dBm0 level of the PCM codec–filter. The +Tx and –Tx inputs provide maximum flexibility for analog interface. All other functions are described in the pin description. MC145508 The MC145508 PCM mono–circuit is intended for byte in- terleaved synchronous applications. The MC145508 has all the features of the MC145507 but internally connects TDC and RDC (see pin description) to the DC pin. One of the five standard frequencies (listed above) should be applied to CCI. The data clock input (DC) can be any frequency between 64 kHz and 4.069 MHz. PIN DESCRIPTIONS DIGITAL VLS Logic Level Select Input and HCMOS Digital Ground VLS controls the logic levels and digital ground reference for all digital inputs and the digital output. These devices can operate with logic levels from full supply (VSS to VDD) or with TTL logic levels using VLS as digital ground. For VLS = VDD, all I/O is full supply (VSS to VDD swing) with CMOS switch points. For VSS < VLS < (VDD – 4 V), all inputs are TTL compatible with VLS being the digital ground while TDD outputs HCMOS levels from VLS to VDD. The pins controlled by VLS are inputs MSI, CCI, TDE, TDC, RCE, RDC, RDD, PDI, and output TDD. MSI Master Synchronization Input MSI is used for determining the sample rate of the transmit side and as a time base for selecting the internal prescale divider for the convert clock input (CCI) pin. The MSI pin should be tied to an 8 kHz clock which may be a frame sync or system sync signal. MSI has no relation to transmit or receive data timing, except for determining the internal trans- mit strobe as described under the TDE pin description. MSI should be derived from the transmit timing in asynchronous applications. In many applications, MSI can be tied to TDE. (MSI is tied internally to TDE in the MC145507/08.) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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