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MC9S08RD60DWE Datasheet(PDF) 96 Page - Motorola, Inc |
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MC9S08RD60DWE Datasheet(HTML) 96 Page - Motorola, Inc |
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96 / 232 page  Carrier Modulator Transmitter (CMT) Module MC9S08RC/RD/RE/RG 96 Freescale Semiconductor The modulator provides a simple method to control protocol timing. The modulator has a minimum resolution of 1.0 µs with an 8 MHz internal bus clock. It can count bus clocks (to provide real-time control) or it can count carrier clocks (for self-clocked protocols). See 7.5.2 Modulator for more details. The transmitter output block controls the state of the infrared out pin (IRO). The modulator output is gated on to the IRO pin when the modulator/carrier generator is enabled. A summary of the possible modes is shown in Table 7-2. 7.5.1 Carrier Generator The carrier signal is generated by counting a register-selected number of input clocks (125 ns for an 8 MHz bus) for both the carrier high time and the carrier low time. The period is determined by the total number of clocks counted. The duty cycle is determined by the ratio of high time clocks to total clocks counted. The high and low time values are user programmable and are held in two registers. An alternate set of high/low count values is held in another set of registers to allow the generation of dual frequency FSK (frequency shift keying) protocols without CPU intervention. NOTE: Only non-zero data values are allowed. The carrier generator will not work if any of the count values are equal to zero. The MCGEN bit in the CMTMSC register must be set and the BASE bit must be cleared to enable carrier generator clocks. When the BASE bit is set, the carrier output to the modulator is held high continuously. The block diagram is shown in Figure 7-3. Table 7-2 CMT Modes of Operation Mode MCGEN Bit(1) NOTES: 1. To prevent spurious operation, initialize all data and control registers before beginning a transmission (MCGEN=1). BASE Bit(2) 2. These bits are not double buffered and should not be changed during a transmission (while MCGEN=1). FSK Bit(2) EXSPC Bit Comment Time 1 0 0 0 fCG controlled by primary high and low registers. fCG transmitted to IRO pin when modulator gate is open. Baseband 1 1 x 0 fCG is always high. IRO pin high when modulator gate is open. FSK 1 0 1 0 fCG control alternates between primary high/low registers and secondary high/low registers. fCG transmitted to IRO pin when modulator gate is open. Extended Space 1x x 1 Setting the EXSPC bit causes subsequent modulator cycles to be spaces (modulator out not asserted) for the duration of the modulator period (mark and space times). IRO Latch 0 x x x IROL bit controls state of IRO pin. |
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