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MC9S08RD60PE Datasheet(PDF) 66 Page - Motorola, Inc

Part # MC9S08RD60PE
Description  Microcontrollers
Download  232 Pages
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MC9S08RD60PE Datasheet(HTML) 66 Page - Motorola, Inc

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Resets, Interrupts, and System Configuration
MC9S08RC/RD/RE/RG
66
Freescale Semiconductor
Figure 5-3 System Reset Status (SRS)
POR — Power-On Reset
Reset was caused by the power-on detection logic. Because the internal supply voltage was ramping
up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVR threshold.
1 = POR caused reset.
0 = Reset not caused by POR.
PIN — External Reset Pin
Reset was caused by an active-low level on the external reset pin.
1 = Reset came from external reset pin.
0 = Reset not caused by external reset pin.
COP — Computer Operating Properly (COP) Watchdog
Reset was caused by the COP watchdog timer timing out. This reset source may be blocked by
COPE = 0.
1 = Reset caused by COP timeout.
0 = Reset not caused by COP timeout.
ILOP — Illegal Opcode
Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP instruction
is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
1 = Reset caused by an illegal opcode.
0 = Reset not caused by an illegal opcode.
ILAD — Illegal Address Access
Reset was caused by an attempt to access a designated illegal address.
1 = Reset caused by an illegal address access
0 = Reset not caused by an illegal address access
Bit 7
6
54321
Bit 0
Read:
POR
PIN
COP
ILOP
ILAD(1)
NOTES:
1. The ILAD bit is only present in 16K and 8K versions of the devices.
0
LVD
0
Write:
Writing any value to SRS address clears COP watchdog timer.
Power-on reset:
1
0
000010
Low-voltage reset:
U
0
000010
Any other reset:
0
(2)
2. Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set;
bits corresponding to sources that are not active at the time of reset will be cleared.
(2)
(2)
(2)
000
U = Unaffected by reset


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