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ALM-2412 Datasheet(PDF) 5 Page - AVAGO TECHNOLOGIES LIMITED

Part No. ALM-2412
Description  GPS LNA-Filter Front-End Module
Download  13 Pages
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Maker  AVAGO [AVAGO TECHNOLOGIES LIMITED]
Homepage  http://www.avagotech.com
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ALM-2412 Datasheet(HTML) 5 Page - AVAGO TECHNOLOGIES LIMITED

 
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5
Figure 2. Demoboard and application schematic diagram
Notes:
 The demoboard of Figure 6 is Rogers® RO4350 with typical Dk = 3.48 (@10GHz).
 L3 and the module’s internal input pre-match form the input matching network. The module has built-in DC-blocking capacitors at the input and
output.
 This circuit demonstrates that very low noise figure is obtainable with standard 0402 chip inductors instead of high-Q wirewound inductors.
 C2 and L2 form a matching network at the output of the LNA stage, which can be tuned to optimize gain and return loss. For example, higher gain
can be obtained by increasing the value of C2 but at the expense of stability. Changing the value of L2 can improve the PCS rejection, but impacts
output return loss.
 L1 is a choke which isolates the demoboard from external disturbances during measurement. It is not needed in actual application. Likewise, C1
and C3 mitigate the effect of external noise pickup on the Vdd and SD lines respectively. These components are not required in actual operation.
 R1 is a stability-enhancing resistor.
 C9 is a DC-blocking capacitor. It is also not required in actual operation.
 Bias control is achieved by either varying the SD voltage with/ without R2, or fixing the SD voltage to Vdd and adjusting R2 for the desired current.
Typical value for R2 is 10k Ohms for 9mA total current at Vdd = 2.85V and Vsd = +2.60V. For applications where it is more appropriate to have SD
(Vsd) connected to Vdd, an 18k Ohms resistor value for R2 is suggested (where Vdd = 2.85V).
 For low-voltage operation such as Vdd = 1.5V or 1.0V, R2 may be omitted and SD (Vsd) connected directly to Vdd.
 The grounding regime for the ALM-2412 is critical to achieving the PCS- and Cell-Band Rejections shown in Figure 9. Please refer to the PCB Land
Patterns section of this document for the exact locations of the grounding vias.
Vdd
3
SD
2
C2
Module outline
1
2,4,5,6,7,9,10,11
Filter
R1
C3
R2
C1
Z1
50-Ohms TL
Input
match
L1
L3
C9
L2
3
8
12
50-Ohms TL
1,4


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