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MC33742 Datasheet(PDF) 13 Page - Motorola, Inc |
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MC33742 Datasheet(HTML) 13 Page - Motorola, Inc |
13 / 52 page MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33742 13 DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted reflect the approximate parameter mean at TA =25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit DIGITAL INTERFACE TIMING (Note 28) SPI Operation Frequency fREQ 0.25 – 4.0 MHz SCLK Clock Period tPCLK 250 – N/A ns SCLK Clock High Time tWSCLKH 125 – N/A ns SCLK Clock Low Time tWSCLKL 125 – N/A ns Falling Edge of CS to Rising Edge of SCLK tLEAD 100 – N/A ns Falling Edge of SCLK to Rising Edge of CS tLAG 100 – N/A ns MOSI to Falling Edge of SCLK tSISU 40 – N/A ns Falling Edge of SCLK to MOSI tSIH 40 – N/A ns MISO Rise Time (Note 29) CL = 220 pF tRSO –25 50 ns MISO Fall Time (Note 29) CL = 220 pF tFSO –25 50 ns Time from Falling or Rising Edges of CS MISO Low Impedance MISO High Impedance tSOEN tSODIS – – – – 50 50 ns Time from Rising Edge of SCLK to MISO Data Valid 0.2 VDD ≤ MISO ≥ 0.8 VDD, CL = 200 pF tVALID –– 50 ns STATE MACHINE TIMING Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command) and Stop Mode Activation (Note 30) tCS-STOP 18–34 µs Interrupt Low-Level Duration Stop Mode tINT 7.0 10 13 µs Internal Oscillator Frequency (Note 31) fOSC – 100 – kHz Watchdog Period Normal and Standby Modes Period 1 Period 2 Period 3 Period 4 tWD 8.58 39.6 88 308 9.75 45 100 350 10.92 50.4 112 392 ms Notes 28. See Figure 4, SPI Timing Diagram, page 17. 29. Not production tested. Guaranteed by design. 30. Not production tested. Guaranteed by design. Detected by V2 OFF. 31. fOSC is indirectly measured (1.0 ms reset) and trimmed. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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