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MC9328MX21VH Datasheet(PDF) 12 Page - Motorola, Inc |
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MC9328MX21VH Datasheet(HTML) 12 Page - Motorola, Inc |
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12 / 106 page  MC9328MX21 Product Preview, Rev. 1.1 12 Freescale Semiconductor Signal Descriptions USBG_ON USB OTG Transceiver ON output signal. This signal is muxed with SLCDC1_DAT9. USBG_FS USB OTG Full Speed output signal. This signal is multiplexed with external transceiver USBG_TXR_INT signal of USB OTG. This signal is muxed with SLCDC1_DAT10. USBH1_RXDP USB Host1 Receive Data Plus input signal. This signal is multiplexed with UART4_RXD and SLCDC1_DAT6. It also provides an alternative multiplex for UART4_RTS, where this signal is selectable by programming the Function Multiplexing Control Register in the System Control chapter. USBH1_RXDM USB Host1 Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT5. It also provides an alternative multiplex for UART4_CTS. USBH1_TXDP USB Host1 Transmit Data Plus output signal. This signal is multiplexed with UART4_CTS and SLCDC1_DAT4. It also provides an alternative multiplex for UART4_RXD, where this signal is selectable by programming the Function Multiplexing Control Register in the System Control chapter. USBH1_TXDM USB Host1 Transmit Data Minus output signal. This signal is multiplexed with UART4_TXD and SLCDC1_DAT3. USBH1_RXDAT USB Host1 Transceiver differential data receive signal. Multiplexed with USBH1_FS. USBH1_OE USB Host1 Output Enable signal. This signal is muxed with SLCDC1_DAT2. USBH1_FS USB Host1 Full Speed output signal. This signal is multiplexed with UART4_RTS and SLCDC1_DAT1 and USBH1_RXDAT. USBH_ON USB Host transceiver ON output signal. This signal is muxed with SLCDC1_DAT0. USBH2_RXDP USB Host2 Receive Data Plus input signal. This signal is multiplexed with CSPI2_SS[1] of CSPI2. USBH2_RXDM USB Host2 Receive Data Minus input signal. This signal is multiplexed with CSPI2_SS[2] of CSPI2. USBH2_TXDP USB Host2 Transmit Data Plus output signal. This signal is multiplexed with CSPI2_MOSI of CSPI2. USBH2_TXDM USB Host2 Transmit Data Minus output signal. This signal is multiplexed with CSPI2_MISO of CSPI2. USBH2_OE USB Host2 Output Enable signal. This signal is multiplexed with CSPI2_SCLK of CSPI2. USBH2_FS USB Host2 Full Speed output signal. This signal is multiplexed with CSPI2_SS[0] of CSPI2. USBG_SCL USB OTG I2C Clock Output signal. This signal is multiplexed with SLCDC1_DAT8. USBG_SDA USB OTG I2C Data Input/Output signal. This signal is multiplexed with SLCDC1_DAT7. USBG_TXR_INT USB OTG transceiver Interrupt input. Multiplexed with USBG_FS. Secure Digital Interface SD1_CMD SD Command bidirectional signal—If the system designer does not want to make use of the internal pull-up, via the Pull-up enable register, a 4.7K–69K external pull up resistor must be added. This signal is multiplexed with CSPI3_MOSI. SD1_CLK SD Output Clock. This signal is multiplexed with CSPI3_SCLK. Table 2. i.MX21 Signal Descriptions (Continued) Signal Name Function/Notes |
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