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MC68EN302 Datasheet(PDF) 2 Page - Motorola, Inc

Part No. MC68EN302
Description  Integrated Multiprotocol Processor with Ethernet
Download  8 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com

MC68EN302 Datasheet(HTML) 2 Page - Motorola, Inc

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The following features are incorporated into the MC68EN302 device:
• Full Complement of Existing Three SCC’s Plus Ethernet Channel
• Ethernet Channel Fully Compliant with IEEE 802.3 Specification.
• Supports Data Rates up to 10 Mbps.
• Supports the “68302” Style Programming Model.
• On-Chip Descriptors Lower Processor Bus Bandwidth Requirements.
• Separate 128 Byte FIFOs for Transmit and Receive.
• Automatic Internal Retransmission (which Frees the Processor Bus).
• Automatic Internal Flushing of Receive FIFO During Collisions (which Frees the Processor Bus).
• Dynamic Bus Sizing Support for 8-Bit Devices
• Glueless Dynamic RAM Controller without External Bus Master
• Address Muxing Support for External Bus Masters Using DRAM Controller
• Fully IEEE 1149.1 JTAG Compliant
• 144 TQFP Package for Up to 25 MHz
The Ethernet controller consists of a Ethernet protocol core, transmit and receive FIFOs, and a 16-bit wide
data/control interface to a 68000 bus (refer to Figure 2). The Ethernet protocol core (EPC) provides
compatibility with the IEEE 802.3 Ethernet standard. The transmit and receive FIFOs allow automatic handling
of collisions and collision fragments by the EPC, and they also provide for bus latency that can be encountered
by the DMA channels. Separate DMA channels are used for transmit and receive data paths. A dual-port RAM
is used for the on-chip buffer descriptors. A buffer descriptor control (BDC) block updates the buffer
descriptors. Control status registers are used for direct control of all of the blocks in the Ethernet controller.
• Does Not Affect Performance of Existing SCCs
• 802.3 MAC Layer Support
• Compatible with 68160 EEST (Twisted Pair/AUI)
• Two Dedicated Ethernet DMA channels, Transmit and Receive
• Full-Duplex (Switched) Ethernet Support
• Up to 10 Mb/s Operation (20 Mb/s Full-Duplex)
• 128-Byte FIFO on both Transmit and Receive
• No CPU or Bus Overhead Required on Rx or Tx Frame Collisions
• 64 entry CAM with Hash Option
• 128 internal Buffer Descriptors
• Performs Framing Functions
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com

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