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DS2482-100 Datasheet(PDF) 3 Page - Dallas Semiconductor |
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DS2482-100 Datasheet(HTML) 3 Page - Dallas Semiconductor |
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3 / 21 page  DS2482-100: Single-Channel 1-Wire Master 3 of 21 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Standard 60 64 68 Write-0 Low Time tW0L Overdrive 7.1 7.5 7.9 µs Standard 5.0 5.3 5.6 Write-0 Recovery Time tREC0 Overdrive 2.8 3.0 3.2 µs Standard 570 600 630 Reset Low Time tRSTL Overdrive 68.4 72 75.6 µs Standard 66.5 70 73.5 Presence Detect Sample Time tMSP Overdrive 7.1 7.5 7.9 µs Standard 7.6 8 8.4 Sampling for Short and Interrupt tSI Overdrive 0.7 0.75 0.8 µs Standard 554.8 584 613.2 Reset High Time tRSTH Overdrive 70.3 74 77.7 µs Presence-Pulse Mask Start tppm1 (Note 8) 9.5 10 10.5 µs Presence-Pulse Mask Stop tppm2 (Note 8) 57 60 63 µs Control Pin (PCTLZ) Output-Low Voltage VOLP VCC = 2.9V, 1.2mA load current 0.4 V Output-High Voltage VOHP 0.4mA load current VCC – 0.5V V I²C Pins (Note 9) See Figure 10 VCC = 2.9V to 3.7V 0.25 × VCC LOW Level Input Voltage VIL VCC = 4.5V to 5.5V -0.5 0.22 × VCC V HIGH Level Input Voltage VIH 0.7 × VCC VCC + 0.5V V Hysteresis of Schmitt Trigger Inputs Vhys 0.05 × VCC V LOW Level Output Voltage at 3mA Sink Current VOL 0.4 V Output Fall Time from VIhmin to VILmax with a Bus Capacitance from 10pF to 400pF tof 60 250 ns Pulse Width of Spikes that are Suppressed by the Input Filter tSP SDA and SCL pins only 50 ns Input Current Each I/O Pin with an Input Voltage Between 0.1VCCmax and 0.9VCCmax Ii (Notes 10, 11) -10 10 µA Input Capacitance Ci (Note 10) 10 pF SCL Clock Frequency fSCL 0 400 kHz Hold Time (Repeated) START Condition. After this Period, the First Clock Pulse is Generated tHD:STA 0.6 µs LOW Period of the SCL Clock tLOW 1.3 µs HIGH Period of the SCL Clock tHIGH 0.6 µs Set-Up Time for a Repeated START Condition tSU:STA 0.6 µs Data Hold Time tHD:DAT (Notes 12, 13) 0.9 µs Data Set-Up Time tSU:DAT (Note 14) 250 ns Set-Up Time for STOP Condition tSU:STO 0.6 µs |
Similar Part No. - DS2482-100 |
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Similar Description - DS2482-100 |
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