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DAC7742 Datasheet(PDF) 4 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation. Click here to check the latest version.
Part No. DAC7742
Description  16-Bit, Single Channel DIGITAL-TO-ANALOG CONVERTER With Internal Reference and Parallel Interface
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Manufacturer  BURR-BROWN [Burr-Brown (TI)]
Direct Link  http://www.burr-brown.com
Logo BURR-BROWN - Burr-Brown (TI)

DAC7742 Datasheet(HTML) 4 Page - Burr-Brown (TI)

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DAC7742
4
SBAS256
www.ti.com
Top View
LQFP
PIN CONFIGURATION
PIN
NAME
DESCRIPTION
1
NC
No Connection
2VSS
Negative Analog Power Supply
3VCC
Positive Analog Power Supply
4VREF
Buffered Output from REFIN; can be used to
drive external devices. Internally, this pin
directly drives the DAC's circuitry.
5ROFFSET
Offsetting Resistor
6
AGND
Analog Ground (Must be tied to analog ground.)
7
AGND
Analog Ground (Must be tied to analog ground.)
8
RFB2
Feedback Resistor 2, used to configure DAC
output range.
9
RFB1
Feedback Resistor 1, used to configure DAC
output range.
10
SJ
Summing Junction of the Output Amplifier
11
VOUT
DAC Voltage Output
12
NC
No Connection
13
NC
No Connection
14
NC
No Connection
15
NC
No Connection
16
DB0
Data Bit 0 (LSB)
17
DB1
Data Bit 1
18
DB2
Data Bit 2
19
DB3
Data Bit 3
20
DB4
Data Bit 4
21
DB5
Data Bit 5
22
DB6
Data Bit 6
23
NC
No Connection
24
NC
No Connection
25
NC
No Connection
26
TEST
Reserved, Connect to DGND
27
DB7
Data Bit 7
PIN DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
NC
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
TEST
NC
1
2
3
4
5
6
7
8
9
10
11
12
NC
V
SS
V
CC
V
REF
R
OFFSET
AGND
AGND
RFB2
RFB1
SJ
V
OUT
NC
48
47
46
45
44
43
42
41
40
39
38
13
14
15
16
17
18
19
20
21
22
23
37
24
DAC7742
28
DB8
Data Bit 8
29
DB9
Data Bit 9
30
DB10
Data Bit 10
31
DB11
Data Bit 11
32
DB12
Data Bit 12
33
DB13
Data Bit 13
34
DB14
Data Bit 14
35
DB15
Data Bit 15 (MSB)
36
NC
No Connection
37
DGND
Digital Ground
38
VDD
Digital Power Supply
39
RST
VOUT reset; active LOW, depending on the state of
RSTSEL, the DAC register is either reset to mid-
scale or min-scale.
40
LDAC
DAC register load control, active LOW. Data is
loaded from the input register to the DAC register.
41
CS
Chip Select, Active LOW
42
R/W
Enabled by CS, controls data read (HIGH) and
write (LOW) from or to the input register.
43
RSTSEL
Reset Select; determines the action of RST. If
HIGH, RST will reset the DAC register to mid-
scale. If LOW, RST will reset the DAC register to
min-scale.
44
REFEN
Enables internal +10V reference (REFOUT), active
LOW.
45
REFOUT
Internal Reference Output
46
REFADJ
Internal Reference Trim. (Acts as a gain
adjustment input when the internal reference is
used.)
47
REFIN
Reference Input
48
NC
No Connection
PIN
NAME
DESCRIPTION


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