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DAC6574 Datasheet(PDF) 20 Page - Texas Instruments

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Part No. DAC6574
Description  QUAD, 10-BIT, LOW-POWER, VOLTAGE OUTPUT, IC INTERFACE DIGITAL-TO-ANALOG CONVERTER
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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DAC6574 Datasheet(HTML) 20 Page - Texas Instruments

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Master Transmitter Writing to a Slave Receiver (DAC6574) in HS Mode
DAC6574
SLAS408 – DECEMBER 2003
When writing data to the DAC6574 in HS-mode, the master begins to transmit what is called the HS-Master
Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master
Code is followed by a NOT acknowledge.
The master then switches to HS-mode and issues a repeated start condition, followed by the address byte (with
R/W = 0) after which the DAC6574 acknowledges by pulling SDA low. This address byte is usually followed by
the control byte, which is also acknowledged by the DAC6574. The LSB of the control byte (PD0-Bit) determines
if the following data is power-down data or regular data.
With (PD0-Bit = 0) the DAC6574 expects to receive data in the following sequence HIGH-BYTE – LOW-BYTE –
HIGH-BYTE – LOW-BYTE...., until a STOP condition or repeated start condition on the I
2C-Bus is recognized
(refer to Table 5 HS-MODE WRITE SEQUENCE - DATA).
With (PD0-Bit = 1) the DAC6574 expects to receive 2 bytes of power-down data (refer to Table 5 HS-MODE
WRITE SEQUENCE - POWER DOWN).
Table 5. Master Transmitter Writes to Slave Receiver (DAC6574) in HS-Mode
HS MODE WRITE SEQUENCE - DATA
Transmitter
MSB
6
5
4
3
2
1
LSB
Comment
Master
Start
Begin sequence
Master
0
0
0
0
1
X
X
X
HS Mode Master Code
No device may acknowledge HS mas-
NONE
Not Acknowledge
ter code
Master
Repeated Start
Master
1
0
0
1
1
A1
A0
R/W
Write addressing (R/W=0)
DAC6574
DAC6574 Acknowledges
Master
0
0
Load 1
Load 0
0
Buff Sel 1
Buff Sel 0
PD0
Control byte (PD0=0)
DAC6574
DAC6574 Acknowledges
Master
D9
D8
D7
D6
D5
D4
D3
D2
Writing data word, MSB
DAC6574
DAC6574 Acknowledges
Master
D1
D0
x
x
x
x
x
x
Writing data word, LSB
DAC6574
DAC6574 Acknowledges
Master
Data or Stop or Repeated Start(1)
Data or done (2)
HS MODE WRITE SEQUENCE - POWER DOWN
Transmitter
MSB
6
5
4
3
2
1
LSB
Comment
Master
Start
Begin sequence
Master
0
0
0
0
1
X
X
X
HS Mode Master Code
No device may acknowledge HS mas-
NONE
Not Acknowledge
ter code
Master
Repeated Start
Master
1
0
0
1
1
A1
A0
R/W
Write addressing (R/W = 0)
DAC6574
DAC6574 Acknowledges
Master
0
0
Load 1
Load 2
0
Buff Sel 1
Buff Sel 0
PD0
Control Byte (PD0=1)
DAC6574
DAC6574 Acknowledges
Master
PD1
PD2
0
0
0
0
0
0
Writing data word, high byte
DAC6574
DAC6574 Acknowledges
Master
0
0
x
x
x
x
x
x
Writing data word, low byte
DAC6574
DAC6574 Acknowledges
Master
Stop or repeated start(1)
Done
(1)
Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.
(2)
Once DAC6574 is properly addressed and control byte is sent, high-byte-low-byte sequences can repeat until a stop or repeated start
condition is received.
20


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