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DAC6574 Datasheet(PDF) 12 Page - Texas Instruments

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Part No. DAC6574
Description  QUAD, 10-BIT, LOW-POWER, VOLTAGE OUTPUT, IC INTERFACE DIGITAL-TO-ANALOG CONVERTER
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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DAC6574 Datasheet(HTML) 12 Page - Texas Instruments

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F/S-Mode Protocol
H/S-Mode Protocol
Start
Condition
SDA
Stop
Condition
SDA
SCL
S
P
SCL
DAC6574
SLAS408 – DECEMBER 2003
THEORY OF OPERATION (continued)
The DAC6574 works as a slave and supports the following data transfer modes, as defined in the I
2C-Bus
Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data
transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in
this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as
H/S-mode. The DAC6574 supports 7-bit addressing; 10-bit addressing and general call address are not
supported.
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 29. All I
2C-compatible devices should
recognize a start condition.
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 30). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 31) by pulling the SDA line low
during the entire high period of the 9
th SCL cycle. Upon detecting this acknowledge, the master knows that
communication link with a slave has been established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from
the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 29). This releases the bus and stops the communication link
with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address.
When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices.
The master generates a start condition followed by a valid serial byte containing H/S master code
00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to
acknowledge the H/S master code, but all devices must recognize it and switch their internal setting to
support 3.4 Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the
start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that
transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the H/S-mode and switches all the
internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated
start conditions should be used to secure the bus in H/S-mode.
Figure 29. START and STOP Conditions
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