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DRV8323RH Datasheet(PDF) 4 Page - Texas Instruments |
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DRV8323RH Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 80 page  1 PGND 30 INHB 2 CPL 29 INLA 3 CPH 28 INHA 4 VCP 27 DVDD 5 VM 26 AGND 6 VDRAIN 25 ENABLE 7 GHA 24 nSCS 8 SHA 23 SCLK 9 GLA 22 SDI 10 SLA 21 SDO Not to scale Thermal Pad 1 PGND 30 INHB 2 CPL 29 INLA 3 CPH 28 INHA 4 VCP 27 DVDD 5 VM 26 AGND 6 VDRAIN 25 ENABLE 7 GHA 24 NC 8 SHA 23 VDS 9 GLA 22 IDRIVE 10 SLA 21 MODE Not to scale Thermal Pad 4 DRV8320, DRV8320R DRV8323, DRV8323R SLVSDJ3 – FEBRUARY 2017 www.ti.com Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions—32-Pin DRV8320 Devices (continued) PIN TYPE (1) DESCRIPTION NAME NO. DRV8320H DRV8320S GLC 15 15 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET. IDRIVE 19 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor. INHA 25 25 I High-side gate driver control input. This pin controls the output of the high-side gate driver. INHB 27 27 I High-side gate driver control input. This pin controls the output of the high-side gate driver. INHC 29 29 I High-side gate driver control input. This pin controls the output of the high-side gate driver. INLA 26 26 I Low-side gate driver control input. This pin controls the output of the low-side gate driver. INLB 28 28 I Low-side gate driver control input. This pin controls the output of the low-side gate driver. INLC 30 30 I Low-side gate driver control input. This pin controls the output of the low-side gate driver. MODE 18 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor. NC 21 — NC No internal connection. This pin can be left floating or connected to system ground. nFAULT 17 17 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor. nSCS — 21 I Serial chip select. A logic low on this pin enables serial interface communication. PGND 31 31 PWR Device power ground. Connect to system ground. SCLK — 20 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. SDI — 19 I Serial data input. Data is captured on the falling edge of the SCLK pin. SDO — 18 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor. SHA 6 6 I High-side source sense input. Connect to the high-side power MOSFET source. SHB 11 11 I High-side source sense input. Connect to the high-side power MOSFET source. SHC 14 14 I High-side source sense input. Connect to the high-side power MOSFET source. SLA 8 8 I Low-side source sense input. Connect to the low-side power MOSFET source. SLB 9 9 I Low-side source sense input. Connect to the low-side power MOSFET source. SLC 16 16 I Low-side source sense input. Connect to the low-side power MOSFET source. VCP 2 2 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins. VDRAIN 4 4 I High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains. VDS 20 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor. VM 3 3 PWR Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and PGND pins. DRV8320RH RHA Package 40-Pin VQFN With Exposed Thermal Pad Top View DRV8320RS RHA Package 40-Pin VQFN With Exposed Thermal Pad Top View |
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