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DRV8323 Datasheet(PDF) 6 Page - Texas Instruments |
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DRV8323 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 80 page  1 CPL 30 ENABLE 2 CPH 29 nSCS 3 VCP 28 SCLK 4 VM 27 SDI 5 VDRAIN 26 SDO 6 GHA 25 nFAULT 7 SHA 24 VREF 8 GLA 23 SOA 9 SPA 22 SOB 10 SNA 21 SOC Not to scale Thermal Pad 1 CPL 30 ENABLE 2 CPH 29 GAIN 3 VCP 28 VDS 4 VM 27 IDRIVE 5 VDRAIN 26 MODE 6 GHA 25 nFAULT 7 SHA 24 VREF 8 GLA 23 SOA 9 SPA 22 SOB 10 SNA 21 SOC Not to scale Thermal Pad 6 DRV8320, DRV8320R DRV8323, DRV8323R SLVSDJ3 – FEBRUARY 2017 www.ti.com Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated DRV8323H RTA Package 40-Pin WQFN With Exposed Thermal Pad Top View DRV8323S RTA Package 40-Pin WQFN With Exposed Thermal Pad Top View (1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain Pin Functions—40-Pin DRV8323 Devices PIN TYPE (1) DESCRIPTION NAME NO. DRV8323H DRV8323S AGND 32 32 PWR Device analog ground. Connect to system ground. CAL 31 31 I Amplifier calibration input. Set logic high to internally short amplifier inputs. CPH 2 2 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins. CPL 1 1 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins. DVDD 33 33 PWR R 3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins. This regulator can source up to 30 mA externally. ENABLE 30 30 I Gate driver enable. When this pin is logic low the device enters a low power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions. GAIN 29 — I Amplifier gain setting. The pin is a 4 level input pin set by an external resistor. GHA 6 6 O High-side gate driver output. Connect to the gate of the high-side power MOSFET. GHB 15 15 O High-side gate driver output. Connect to the gate of the high-side power MOSFET. GHC 16 16 O High-side gate driver output. Connect to the gate of the high-side power MOSFET. GLA 8 8 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET. GLB 13 13 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET. GLC 18 18 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET. IDRIVE 27 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor. INHA 34 34 I High-side gate driver control input. This pin controls the output of the high-side gate driver. INHB 36 36 I High-side gate driver control input. This pin controls the output of the high-side gate driver. INHC 38 38 I High-side gate driver control input. This pin controls the output of the high-side gate driver. INLA 35 35 I Low-side gate driver control input. This pin controls the output of the low-side gate driver. INLB 37 37 I Low-side gate driver control input. This pin controls the output of the low-side gate driver. INLC 39 39 I Low-side gate driver control input. This pin controls the output of the low-side gate driver. MODE 26 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor. nFAULT 25 25 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor. nSCS — 29 I Serial chip select. A logic low on this pin enables serial interface communication. PGND 40 40 PWR Device power ground. Connect to system ground. SCLK — 28 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. SDI — 27 I Serial data input. Data is captured on the falling edge of the SCLK pin. SDO — 26 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor. |
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Similar Description - DRV8323 |
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