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DDC316 Datasheet(PDF) 6 Page - Texas Instruments |
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DDC316 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 28 page  TIMING DIAGRAMS CONV DVALID CLK t CLK t CLKPW DCLK DOUT (1) SideBData SideAData t CLKPW t DOHD t DOPD t DCLKPW t DCLKPW t DCDV t DVDO t INTA t DCLK t CNDC t CNDC t MEAS t INTB MSB LSB NOTE:(1)DOUT1inTDMdataoutputmode;DOUT1throughDOUT4inparalleldataoutputmode. DIN t DIDC t DCDI TIMING REQUIREMENTS FOR Figure 1 DDC316 SBAS370A – MARCH 2008 – REVISED APRIL 2009......................................................................................................................................................... www.ti.com Figure 1. Serial Interface Timing At TA = 0°C to +70°C and DVDD = 3V to 3.6V, unless otherwise noted. SYMBOL DESCRIPTION MIN TYP MAX UNIT tCLK CLK period (1/fCLK) 25 1000 ns tCLKPW CLK pulse width, positive or negative 0.4 tCLK periods HI_SPEED bit = 0 400 1000 tCLK periods HI_SPEED bit = 0, CLK = 40MHz 10 25 µs tINTA,B Integration time for sides A and B HI_SPEED bit = 1 800 40,000 tCLK periods HI_SPEED bit = 1, CLK = 40MHz 20 1000 µs HI_SPEED bit = 0 274 tCLK periods Time required to perform tMEAS measurement HI_SPEED bit = 1 544 tCLK periods tDIDC Setup time from DIN to rising edge of DCLK 2 ns tDCDI Hold time for DIN after rising edge of DCLK 0 ns tDVDO (1) Falling edge of DVALID to valid DOUT 6 10 ns tDCDV (1) Falling edge of first DCLK to rising edge of DVALID 19 ns tDCLK DCLK period (1/fDCLK) 25 ns tDCLKPW DCLK pulse width, positive or negative 0.4 tDCLK periods tDOPD (1) Propagation delay from the falling edge of DCLK to valid DOUT1 21 ns Hold time during which previous DOUT1 is valid after falling edge of tDOHD (1) 5 ns DCLK tCNDC Time between CONV toggle and data retrieval 5 ns (1) Output load = 100k Ω || 10pF 6 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): DDC316 |
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Similar Description - DDC316_17 |
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