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DAC8775 Datasheet(PDF) 42 Page - Texas Instruments |
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DAC8775 Datasheet(HTML) 42 Page - Texas Instruments |
42 / 81 page Output Change Slew Time = Step Size.Update Clock Frequency.LSB Size 42 DAC8775 SLVSBY7 – FEBRUARY 2017 www.ti.com Product Folder Links: DAC8775 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated If enabled, the chip must have an SPI frame with 0x10 as the write address byte written to the device within the programmed timeout period. Otherwise, the ALARM pin asserts low and the WDT bit (address 0x0B) of the status register is set to '1'. The WDT bit is set to '0' with a software/hardware reset, or by disabling the watchdog timer (WEN = '0'), or powering down the device. When using multiple DAC8775 devices in a daisy-chain configuration, the open-drain ALARM pins of all devices can be connected together to form a wired-AND network. The watchdog timer can be enabled in any number of the devices in the chain although enabling it in one device in the chain should be sufficient. The wired-AND ALARM pin may get pulled low because of the simultaneous presence of different trigger conditions in the devices in the daisy-chain. The host processor should read the status register of each device to know all the fault conditions present in the chain. 8.3.14 Programmable Slew Rate The slew rate control feature allows the user to control the rate at which the output voltage or current changes. This feature is disabled by default and can be enabled for the selected channel by writing logic '1' to the SREN bit at address 0x04 (see Table 6). With the slew rate control feature disabled, the output changes smoothly at a rate limited by the output drive circuitry and the attached load. With this feature enabled, the output does not slew directly between the two values. Instead, the output steps digitally at a rate defined by bits [2:0] (SR_STEP) and bits [3:0] (SRCLK_RATE) on address 0x04 (see Table 6). SR_RATE defines the rate at which the digital slew updates; SRCLK_STEP defines the amount by which the output value changes at each update. Table 6 shows different settings for SRCLK_STEP and SR_RATE. The time required for the output to slew over a given range can be expressed as Equation 8: (8) Where: • Slew Time is expressed in seconds • Output Change is expressed in amps (A) for current output mode or volts (V) for voltage output mode When the slew rate control feature is enabled, the output changes happen at the programmed slew rate. This configuration results in a staircase formation at the output. If the CLR pin is asserted, the output slews to the zero-scale value at the programmed slew rate. When a new DAC data is written, the output starts slewing to the new value at the slew rate determined by the current DAC code and the new DAC data. The update clock frequency for any given value is the same for all output ranges. The step size, however, varies across output ranges for a given value of step size because the LSB size is different for each output range. Note that disabling the slew rate feature while the DAC is executing the slew rate command will abort the slew rate operation and the DAC output will stay at the last code after which the slew rate disable command was acknowledged. 8.3.15 HART Interface On the DAC8775, digital communication such as HART can be modulated onto the input signal for each channel. In the case where the RANGE (address 0x04) bits are programmed such that the IOUT_x is enabled, the external HART signal (ac voltage; 500 mVPP, 1200 Hz and 2200 Hz) can be capacitively coupled in through the HARTIN_x pin and transferred to a current that is superimposed on the current output. The HARTIN_x pin has a typical input impedance of 20 kΩ to 30 kΩ, depending on the selected current output range, which together with the input capacitor used to couple the external HART signal into the HARTIN_x pin can be used to form a high- pass filter to attenuate frequencies below the HART bandpass region. In addition to this filter, an external passive filter is recommended to complete the filtering requirements of the HART specifications. Figure 105 illustrates the output current versus time operation for a typical HART interface. |
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