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X1228 Datasheet(PDF) 3 Page - Xicor Inc.

Part No. X1228
Description  Real Time Clock/Calendar/CPU Supervisor with EEPROM
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Maker  XICOR [Xicor Inc.]
Homepage  http://www.xicor.com
Logo XICOR - Xicor Inc.

X1228 Datasheet(HTML) 3 Page - Xicor Inc.

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X1228
REV 1.3 3/24/04
Characteristics subject to change without notice.
3 of 31
www.xicor.com
PIN ASSIGNMENTS
Pin Number
SOIC/TSSOP
Symbol
Brief Description
1X1
X1. The X1 pin is the input of an inverting amplifier. An external 32.768kHz quartz crystal
is used with the X1228 to supply a timebase for the real time clock. The recommended
crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is included to form
a complete oscillator circuit. Care should be taken in the placement of the crystal and the
layout of the circuit. Plenty of ground plane around the device and short traces to X1 are
highly recommended. See Application section for more recommendations.
2X2
X2. The X2 pin is the output of an inverting amplifier. An external 32.768kHz quartz
crystal is used with the X1228 to supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is
included to form a complete oscillator circuit. Care should be taken in the placement of the
crystal and the layout of the circuit. Plenty of ground plane around the device and short traces
to X2 are highly recommended. See Application section for more recommendations.
6
RESET
RESET Output – RESET. This is a reset signal output. This signal notifies a host
processor that the watchdog time period has expired or that the voltage has dropped
below a fixed VTRIP threshold. It is an open drain active LOW output. Recommended
value for the pullup resistor is 5K Ohms. If unused, tie to ground.
7VSS
VSS.
8
SDA
Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or open
collector outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up resistor. The output circuitry controls
the fall time of the output signal with the use of a slope controlled pull-down. The circuit
is designed for 400kHz 2-wire interface speeds.
9
SCL
Serial Clock (SCL). The SCL input is used to clock all data into and out of the device.
The input buffer on this pin is always active (not gated).
12
PHZ/IRQ
Programmable Frequency/Interrupt Output – PHZ/IRQ. This is either an output from
the internal oscillator or an interrupt signal output. It is a CMOS output.
When used as frequency output, this signal has a frequency of 32.768kHz, 4096Hz, 1Hz
or inactive.
When used as interrupt output, this signal notifies a host processor that an alarm has
occurred and an action is required. It is an active LOW output.
The control bits for this function are FO1 and FO0 and are found in address 0011h of the
Clock Control Memory map. See “Programmable Frequency Output Bits—FO1, FO0” on
page 14.
13
VBACK
VBACK. This input provides a backup supply voltage to the device. VBACK supplies
power to the device in the event the VCC supply fails. This pin can be connected to a
battery, a Supercap or tied to ground if not used.
14
VCC
VCC.


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