VIC068A
7
Theory of Operation
The VIC068A is an interface between a local CPU bus and the
VMEbus. The local bus interface of the VIC068A emulates Mo-
torola’s family of 32-bit CISC processor interfaces. Other pro-
cessors can easily be adapted to interface to the VIC068A
using the appropriate logic.
Resetting the VIC068A
The VIC068A can be reset by any of three distinct reset con-
ditions:
Internal Reset. This reset is the most common means of re-
setting the VIC068A. It resets select register values and all
logic within the device.
System Reset. This reset provides a means of resetting the
VIC068A through the VMEbus backplane. The VIC068A may
also signal a SYSRESET* by writing a configuration register.
Global Reset. This provides a complete reset of the VIC068A.
This reset resets all of the VIC068A’s configuration registers.
This reset should be used with caution since SYSCLK is not
driven while a global reset is in progress.
All three reset options are implemented in a different manner
and have different effects on the VIC068A configuration regis-
ters.
VIC068A VMEbus System Controller
The VIC068A is capable of operating as the VMEbus system
controller. It provides VMEbus arbitration functions, including:
• Priority, round-robin, and single-level arbitration schemes
• Driving IACK* Daisy-Chain
• Driving BGiOUT* Daisy-Chain (All four levels)
• Driving SYSCLK output
• VMEbus arbitration timeout timer
The System controller functions are enabled by the SCON* pin
of the VIC068A. When strapped LOW, the VIC068A functions
as the VMEbus system controller.
VIC068A VMEbus Master Cycles
The VIC068A is capable of becoming the VMEbus master in
response to a request from local resources. In this situation,
the local resource requests that a VMEbus transfer is desired.
The VIC068A makes a request for the VMEbus. When the
VMEbus is granted to the VIC068A, it then performs the trans-
fer and acknowledges the local resource and the cycle is com-
plete. The VIC068A is capable of all four VMEbus request lev-
els. The following release modes are supported:
• Release on request (ROR)
• Release when done (RWD)
• Release on clear (ROC)
• Release under RMC* control
• Bus capture and hold (BCAP)
The VIC068A supports A32, A24, and A16, as well as user-de-
fined address spaces.
Master Write-Posting
The VIC068A is capable of performing master write-posting
(bus decoupling). In this situation, the VIC068A acknowledges
the local resource
immediately after the request to the
VIC068A is made, thus freeing the local bus. The VIC068A
latches the local data to be written and performs the VMEbus
transfer without the local resource having to wait for VMEbus
arbitration.
Indivisible Cycles
Read-modify-write cycles and indivisible multiple-address cy-
cles (EMACS) are easily performed using the VIC068A. Sig-
nificant control is allowed to:
• Requesting the VMEbus on the assertion of RMC* indepen-
dent of MWB* (this prevents any slave access from inter-
rupting local indivisible cycles)
• Stretching the VMEbus AS*
• Making the above behaviors dependent on the local SIZi signals
Deadlock Condition
If a master operation is attempted when a slave operation to
the same module is in progress, a deadlock condition has oc-
curred. The VIC068A will signal a deadlock condition by as-
serting the DEDLK* signal. This should be used by the local
resource requesting the VMEbus to try the transfer after the
slave access has completed.
Self-Access Condition
If the VIC068A, while it is VMEbus master, has a slave select
signaled, a self access is said to have occurred. The VIC068A
will issue a BERR*, which in turn will cause a LBERR* to be
asserted.
VIC068A VMEbus Slave Cycles
The VIC068A is capable of operating as a VMEbus slave con-
troller. The VIC068A contains a highly programmable environ-
ment to allow for a wide variety of slave configurations. The
VIC068A allows for:
• D32, D16, or D8 configuration
• A32, A24, A16, or user-defined address spaces
• Programmable block transfer support including:
— DMA-type block transfer (PAS* and DSACKi* held
asserted)
— non-DMA-type block transfer (toggle PAS* and DSACKi*)
— No support for block transfer
• Programmable data acquisition delays
• Programmable PAS* and DS* timing
• Restricted slave accesses (supervisory accesses only)
When a slave access is required, the VIC068A will request the
local bus. When local bus mastership is obtained, the VIC068A
will read or write the data to/from the local resource and assert
the DTACK* signal to complete the transfer.
Slave Write-Posting
The VIC068A is capable of performing a slave write-post op-
eration (bus decoupling). When enabled, the VIC068A latches
the data to be written and acknowledge the VMEbus (asserts
DTACK*) immediately thereafter. This prevents the VMEbus
from having to wait for local bus access.
Address Modifier (AM) Codes
The VIC068A encodes and decodes the VMEbus address
modifier codes. For VMEbus master accesses, the VIC068A
encodes the appropriate AM codes through the VIC068A FCi
and ASIZi signals, as well as the block transfer status. For
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