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C8051F588-IM Datasheet(PDF) 3 Page - Silicon Laboratories
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C8051F588-IM Datasheet(HTML) 3 Page - Silicon Laboratories
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W7206F2 Silicon Labs Bulletin rev N
The information contained in this document is PROPRIETARY to Silicon Laboratories, Inc. and shall not be reproduced or used in
part or whole without Silicon Laboratories’ written consent. The document is uncontrolled if printed or electronically saved. Pg 5
Limited cold programming temperature range for industrial grade (-I) devices
– Added a note regarding programming at cold temperatures on –I devices to section 15.1 Programming
The Flash Memory on page 138 and added Temperature during Programming Operations specification to
Table 5.5 Flash Electrical Characteristics on page 48.
This specification was previously documented in the errata and has now been moved to the data sheet. It
has been removed from the errata.
For –I (Industrial Grade) parts, parts programmed at a cold temperature below 0 °C may exhibit weakly
programmed flash memory bits. If programmed at 0 °C or higher, there is no problem reading Flash across
the entire temperature range of -40 °C to 125 °C. This temperature restriction does not apply to –A
(Automotive Grade) devices.
VREF pin cannot operate as open-drain when VDD selected as reference source
– Added a note regarding P0.0/VREF when VDD is used as the reference to Table 20.1 Port I/O Assignment
for Analog Functions on page 191 and to the description of the REFSL bit in SFR Definition 8.1 REF0CN
register on page 76.
This issue was previously documented in the errata and has now been moved to the data sheet. It has
been removed from the errata.
If VDD is selected as the voltage reference in the REF0CN register and the ADC is enabled in the
ADC0CN register, the P0.0/VREF pin cannot operate as a general purpose I/O pin in open-drain
mode. With the above settings, this pin can operate in push-pull output mode or as an analog
GPIO may have indeterminate state for fast VIO ramp
– Added a note regarding a potential unknown state on GPIO during power up if VIO ramps significantly
before VDD to section 20 Port Input/Output on page 188 and section 17 Reset Sources on page 152.
Note: When VIO rises faster than VDD, which can happen when VREGIN and VIO are tied together, a delay
created between GPIO power (VIO) and the logic controlling GPIO (VDD) results in a temporary unknown
state at the GPIO pins. Cross coupling VIO and VDD with a 4.7 μF capacitor mitigates the root cause of the
problem by allowing VIO and VDD to rise at the same rate.
Set FLEWT bit before writing or erasing flash
– Added steps to set the FLEWT bit in the SFR Definition 15.3 FLSCL register on page 147 in section 15.1.3
Flash Erase Procedure on page 139, section 15.1.4 Flash Write Procedure on page 139, and section 15.1.5
Flash Write Optimization on page 140.
This requirement was previously documented in the bit description for the FLEWT bit, and it’s been
added to the procedures to make it more prominent.
FLEWT Flash Erase Write Time Control.
This bit should be set to 1b before Writing or Erasing Flash.
0: Short Flash Erase / Write Timing.
1: Extended Flash Erase / Write Timing.
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