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C8051F588-IM Datasheet(PDF) 5 Page - Silicon Laboratories
SILABS [Silicon Laboratories]
C8051F588-IM Datasheet(HTML) 5 Page - Silicon Laboratories
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W7206F2 Silicon Labs Bulletin rev N
The information contained in this document is PROPRIETARY to Silicon Laboratories, Inc. and shall not be reproduced or used in
part or whole without Silicon Laboratories’ written consent. The document is uncontrolled if printed or electronically saved. Pg 7
UART RX may overrun on simultaneous FIFO read/write
– Added notes regarding UART RX behavior in section 24.3.2 Data Reception on page 260.
Note: The UART Receive FIFO pointer can be corrupted if the UART receives a byte and firmware reads a
byte from the FIFO at the same time. When this occurs, firmware will lose the received byte and the FIFO
receive overrun flag (OVR0) will also be set to 1. Systems using the UART Receive FIFO should ensure that
the FIFO isn’t accessed by hardware and firmware at the same time. In other words, firmware should
ensure to read the FIFO before the next byte is received.
Included crystal oscillator electrical characteristics
– Added Table 5.8 Crystal Oscillator Electrical Characteristics on page 50. The table includes crystal
frequency and crystal drive current specifications.
This information was not documented in the data sheet before.
Use software-controlled startup sequence to reliably start crystal oscillator
– Added a note regarding surface mount crystals and drive current in section 19.4.1 External Crystal
Example on page 185
Note: Small surface mount crystals can have maximum drive level specifications that are exceeded by the
above XFCN recommendations. In these cases, a software-controlled startup sequence may be used to
reliably start the crystal using a higher XFCN setting, and then lowering the XFCN setting once the
oscillator has started to reduce the drive level and prevent damage or premature aging of the crystal. In
all cases, the drive level should be measured to ensure that the crystal is being driven within its
operational guidelines as part of robust oscillator system design. Contact technical support for additional
details and recommendations if using surface mount crystals with these devices.
No delay requirement after enabling VDD monitor and before enabling it as reset source
– Removed recommendations to introduce a delay after enabling the VDD Monitor before enabling it as a
reset source in 17.2 Power-Fail Reset/V
Monitor on page 154.
The step "If necessary, wait for VDD monitor to stabilize" in the previous data sheet was removed.
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