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C8051F563-IQ Datasheet(PDF) 1 Page - Silicon Laboratories |
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C8051F563-IQ Datasheet(HTML) 1 Page - Silicon Laboratories |
1 / 5 page Bulletin #1409081 _____________________________________________________________________________________________________ W7206F2 Silicon Labs Bulletin rev I The information contained in this document is PROPRIETARY to Silicon Laboratories, Inc. and shall not be reproduced or used in part or whole without Silicon Laboratories’ written consent. The document is uncontrolled if printed or electronically saved. Pg 3 User Registration Register today to create your account on Silabs.com. Your personalized profile allows you to receive technical document updates, new product announcements, “how-to” and design documents, product change notices (PCN) and other valuable content available only to registered users. http://www.silabs.com/profile Bulletin Date: 9/8/2014 Bulletin Effective Date: 9/8/2014 Title: C8051F55x_C8051F56x_C8051F57x_Rev1.2_Data_Sheet_Product_Change_Notice Originator: Greg Hodgson Phone: 512-523-5766 Dept: Marketing Customer Contact: Kathy Haggar Phone: 512-532-5261 Dept: Sales Bulletin Details Description: Silicon Labs is pleased to announce that version 1.2 of the C8051F55x/56x/57x data sheet is now available. The revision includes: Power-On Reset may fail for devices shipped prior to date code 1124 - Added a note regarding an issue with /RST low time on some older devices to “Power-On Reset” on page 140. This issue was previously documented in the errata and has now been moved to the data sheet. It has been removed from the errata. Note: For devices with a date code before year 2011, work week 24 (1124), if the /RST pin is held low for more than 1 second while power is applied to the device, and then /RST is released, a percentage of devices may lock up and fail to execute code. Toggling the /RST pin does not clear the condition. The condition is cleared by cycling power. Most devices that are affected will show the lock up behavior only within a narrow range of temperatures (a 5 to 10 degrees C window). Parts with a date code of year 2011, work week 24 (1124) or later do not have any restrictions on /RST low time. The date code of a device is a four-digit number on the bottom-most line of each device with the format YYWW, where YY is the two-digit calendar year and WW is the two digit work week. Use VDD Monitor low threshold setting during normal operation – Added the note regarding the voltage regulator and VDD monitor in the high setting from “Power-Fail Reset/VDD Monitor” on page 140 to “Voltage Regulator (REG0)” on page 80 and “VDD Maintenance and the VDD monitor” on page 130. This note already existed in the data sheet in the Reset Sources chapter, and it’s been added to additional locations to make it more prominent. Note: The output of the internal voltage regulator is calibrated by the MCU immediately after any reset event. The output of the un-calibrated internal regulator could be below the high threshold setting of the VDD Monitor. If this is the case and the VDD Monitor is set to the high threshold setting and if the MCU receives a non-power on reset (POR), the MCU will remain in reset until a POR occurs (i.e., VDD Monitor will keep the device in reset). A POR will force the VDD Monitor to the low threshold setting which is guaranteed to be below the un-calibrated output of the internal regulator. The device will then exit reset and resume normal operation. It is for this reason Silicon Labs strongly recommends that the VDD Monitor is always left in the low threshold setting (i.e. default value upon POR). |
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