6 Bit Digital Step Attenuator

1 MHz to 4000 MHz

7

Rev 1, June 2015

IDTF1912NCGI

Datasheet

Figure 2 - Serial Register Timing Diagram

Note - When Latch enable is high, the shift register is disabled and DATA is NOT continuously clocked into

the shift register which minimizes noise. It is recommended that Latch enable be left high when the device is

Table 3 - Serial Mode Timing Table

Interval

Symbol

Description

Min

Spec

Max

Spec

Units

Parallel to Serial Setup Time - From rising edge

100

ns

Clock high pulse width

10

ns

LE Setup Time - From the rising edge of CLK

pulse for D0 to LE rising edge minus half the

clock period.

10

ns

LE pulse width

30

ns

Data Setup Time - From the starting edge of

Data bit to rising edge of CLK

10

ns

Data Hold Time - From rising edge of CLK to

falling edge of the Data bit.

10

ns