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LM78 Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part No. LM78
Description  Microprocessor System Hardware Monitor
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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LM78 Datasheet(HTML) 3 Page - National Semiconductor (TI)

 
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Pin Descriptions
Pin
Name(s)
Pin
Number
Number
of Pins
Type
Description
IORD
1
1
Digital Input
An active low standard ISA bus I/O Read Control.
IOWR
2
1
Digital Input
An active low standard ISA bus I/O Write Control.
SYSCLK
3
1
Digital Input
The reference clock for the ISA bus. Typically ranges from 4.167 MHz to
8.33 MHz. The minimum clock frequency this input can handle is 1 Hz.
D7–D0
4–11
8
Digital I/O
Bi-directional ISA bus Data lines. D0 corresponds to the low order bit,
with D7 the high order bit.
V
CC (+5V)
12
1
POWER
+5V V
CC power. Bypass with the parallel combination of 10 µF
(electolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors.
GNDD
13
1
GROUND
Internally connected to all digital circuitry.
SMI__IN
14
1
Digital Input
Chainable SMI (System Management Interrupt) Input. This is an active
low input that propagates the SMI signal to the SMI output of the LM78
via SMI Mask Register Bit 6 and SMI enable Bit 1 of the Configuration
Register.
Chassis
Intrusion
15
1
Digital I/O
An active high input from an external circuit which latches a Chassis
Intrusion event. This line can go high without any clamping action
regardless of the powered state of the LM78. The LM78 provides an
internal open drain on this line, controlled by Bit 7 of NMI Mask Register
2, to provide a minimum 20 ms reset of this line.
Power
Switch
Bypass
16
1
Digital Output
An active low push-pull output intended to drive an external P-channel
power MOSFET for software power control.
FAN3–FAN1
17–19
3
Digital Input
0V to +5V amplitude fan tachometer input.
SCL
20
1
Digital Input
Serial Bus Clock.
SDA
21
1
Digital I/O
Serial Bus bidirectional Data.
RESET
22
1
Digital Output
Master Reset, 5 mA driver (open drain), active low output with a 20 ms
minimum pulse width. Available when enabeld via Bit 7 in SMI Mask
Register 2.
NTEST
23
1
Test Output
NAND Tree totem-pole output that provides board-level connectivity
testing. Refer to Section 11.0 on NAND Tree testing.
GNDA
24
1
GROUND
Internally connected to all analog circuitry. The ground reference for all
analog inputs.
−IN6
25
1
Analog Input
Ground-referred inverting op amp input. Refer to Section 4.0, “ANALOG
INPUTS”.
FB6
26
1
Analog Output
Output of inverting op amp for Input 6. Refer to section 4.0, “ANALOG
INPUTS”.
FB5
27
1
Analog Output
Output of inverting op amp for Input 5. Refer to section 4.0, “ANALOG
INPUTS”.
−IN5
28
1
Analog Input
Ground-referred inverting op amp input. Refer to Section 4.0, “ANALOG
INPUTS”.
IN4–IN0
29–33
5
Analog Input
0V to 4.096V FSR Analog Inputs.
VID3–VID0
34–37
4
Digital Input
Voltage Supply readouts from P6. This value is read in the VID/Fan
Divisor Register.
BTI
38
1
Digital Input
Board Temperature Interrupt driven by O.S. outputs of additional
temperature sensors such as LM75. Provides internal pull-up of 10 k
Ω.
NMI/IRQ
39
1
Digital Output
Non-Maskable Interrupt (open source)/Interrupt Request (open drain).
The mode is selected with Bit 5 of the Configuration Register and the
output is enabled when Bit 2 of the Configuration Register is set to 1.
The default state is disabled and IRQ mode.
SMI
40
1
Digital Output
System Management Interrupt (open drain). This output is enabled when
Bit 1 in the Configuration Register is set to 1. The default state is
disabled.
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