CN-0385

Circuit Note

Rev. 0 | Page 6 of 13

Each channel functions similarly to an RC circuit having an

associated time constant that dominates settling time.

Dynamically switching channels complicates signal settling;

at the time channels are switched, the difference between the

previous output and the current input produces a kickback

transient. This kickback is similar to the one that occurs at the

input to the AD4003 as it enters the acquisition phase. For a

more detailed description, see the Analog Dialogue article,

Front-End Amplifier and RC Filter Design for a Precision SAR

Analog-to-Digital Converter.

The circuit in Figure 4 was simulated using NI Multisim™, as

shown in Figure 5, with the following component values from

the respective device data sheets:









(1.25 GΩ) to be omitted from simulation.

Figure 5. Multisim Settling Time Model of the ADG5207

The simulation results are shown in Figure 6. The time required

for the output of the ADG5207 to settle to 0.001% of 10 V is

Figure 6. Settling Time Waveforms for the ADG5207 Simulation Model

Settling Time of the AD8251 and AD8475

The AD8251 data sheet specifies its settling time for a variety of

input voltage step sizes down to a 0.001% error for each gain

configuration. Given a load of 10 kΩ and gain setting of 1, the

AD8251 can settle a 20 V step at its output to 0.001% in

approximately 1 μs. The gain of 1 setting requires the most

settling time; therefore, the settling time analysis uses 1 μs.

However, the 1 μs number may not be accurate when the

AD8251 is driving one of the inputs of the AD8475, which has

an input impedance of 2.92 kΩ instead of 10 kΩ. It is also not

possible to ascertain settling time of the AD8251 to 18-bit

resolution, because of the nonlinear relationship between

settling time and precision. Therefore, the best settling time

estimation is 0.001% error (or 16-bit resolution).

The AD8475 has a settling time specification of 50 ns to 0.001%

for a 2 V differential output step. The maximum voltage step size

expected on the outputs of the AD8475 is twice the reference

time is proportional to the output voltage step, the settling time to

0.001% (16 bits) for an 8 V step is approximately 200 ns (4 × 50 ns).

The settling time of each amplifier is, therefore,





Settling Time of the RC Noise Filter and AD4003

Figure 7 shows the equivalent circuit of the inputs of the AD4003.

primarily the pin capacitance, and is ignored. The values for

these components are as follows:









Figure 7. Settling Time Model of the AD4003 and RC Noise Filter

The AD4003 employs an internal capacitive DAC and a charge

redistribution algorithm to determine its output code. The

conversion process contains two phases, acquisition and

conversion. During acquisition, the capacitive DAC is

connected to the input terminals of the AD4003. During

conversion, it is disconnected from the input terminals, and

internal logic performs the charge-redistribution algorithm.

Compared to other PulSAR ADCs, the AD4003 has a much

V2

–10V

XSC1

AB C D

G

T

3.5pF

V1

+10V

3.5pF

S1

OUTPUT

MUX CONTROL

+–

1

2

1

2

250Ω

CD1

36pF

C1

2pF

56pF

56pF

100Ω

100Ω

250Ω

4

3

2

1

050

100

TIME (ns)

150

200

250

300

–50

0

10

5

0

–5

–10

188ns, +10V

0ns, –10V

OUTPUT (V)

MUX CTR (V)

REF

D1

D2

IN+ OR IN–

GND

GND

GND

EXT

AD4003