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AD7403BRIZRL7 Datasheet(PDF) 15 Page  Analog Devices 

AD7403BRIZRL7 Datasheet(HTML) 15 Page  Analog Devices 
15 / 25 page AD7403 Data Sheet TERMINOLOGY Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are specified negative full scale, −250 mV (VIN+ − VIN−), Code 7168 for the 16bit level, and specified positive full scale, +250 mV (VIN+ − VIN−), Code 58,368 for the 16bit level. Offset Error Offset error is the deviation of the midscale code (32,768 for the 16bit level) from the ideal VIN+ − VIN− (that is, 0 V). Gain Error The gain error includes both positive fullscale gain error and negative fullscale gain error. Positive fullscale gain error is the deviation of the specified positive fullscale code (58,368 for the 16bit level) from the ideal VIN+ − VIN− (250 mV) after the offset error is adjusted out. Negative fullscale gain error is the deviation of the specified negative fullscale code (7168 for the 16bit level) from the ideal VIN+ − VIN− (−250 mV) after the offset error is adjusted out. SignaltoNoiseandDistortion Ratio (SINAD) SINAD is the measured ratio of signal to noise and distortion at the output of the ADC. The signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), including harmonics, but excluding dc. SignaltoNoise Ratio (SNR) SNR is the measured ratio of signal to noise at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process: the greater the number of levels, the smaller the quantization noise. The theoretical signaltonoise ratio for an ideal Nbit converter with a sine wave input is given by SignaltoNoise Ratio = (6.02N + 1.76) dB Therefore, for a 12bit converter, the SNR is 74 dB. Isolation Transient Immunity The isolation transient immunity specifies the rate of rise and fall of a transient pulse applied across the isolation boundary, beyond which clock or data is corrupted. The AD7403 was tested using a transient pulse frequency of 100 kHz. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. It is defined as 1 6 5 4 3 2 V V V V V V THD 2 2 2 2 2 log 20 (dB) + + + + = where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise (SFDR) Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Effective Number of Bits (ENOB) ENOB is defined by ENOB = (SINAD − 1.76)/6.02 bits Noise Free Code Resolution Noise free code resolution represents the resolution in bits for which there is no code flicker. The noise free code resolution for an Nbit converter is defined as Noise Free Code Resolution (Bits) = log2(2N/PeaktoPeak Noise) The peaktopeak noise in LSBs is measured with VIN+ = VIN− = 0 V. CommonMode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at ±250 mV frequency, f, to the power of a +250 mV peaktopeak sine wave applied to the commonmode voltage of VIN+ and VIN− of frequency, fS, as CMRR (dB) = 10 log(Pf/PfS) where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output. Power Supply Rejection Ratio (PSRR) Variations in power supply affect the fullscale transition but not the linearity of the converter. PSRR is the maximum change in the specified fullscale (±250 mV) transition point due to a change in power supply voltage from the nominal value. Rev. B  Page 14 of 24 
