AD7172-2BRUZ-RL7 datasheet(11/61 Pages) AD

Part #	AD7172-2BRUZ-RL7

Description	True rail-to-rail analog and reference input buffers

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Manufacturer	AD [Analog Devices]

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AD7172-2

Data Sheet

Rev. A | Page 10 of 60

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

12

11

REF–

REF+

REFOUT

AVDD1

AVSS

REGCAPA

AIN4

AVDD2

XTAL1

DIN

DOUT/RDY

XTAL2/CLKIO

20

21

22

23

24

19

18

17

16

15

14

13

AIN2

AIN1

AIN0

REGCAPD

GPIO0

GPIO1

DGND

IOVDD

SCLK

CS

SYNC/ERROR

AIN3

AD7172-2

TOP VIEW

(Not to Scale)

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

1

AIN4

AI

Analog Input 4. Analog Input 4 is selectable through the crosspoint multiplexer.

2

REF−

AI

Reference Input Negative Terminal. REF− can span from AVSS to AVDD1 − 1 V.

3

REF+

AI

Reference Input Positive Terminal. An external reference can be applied between REF+ and REF−. REF+

can span from AVSS + 1 V to AVDD1.The device functions with a reference magnitude from 1 V to

AVDD1.

4

REFOUT

AO

Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS.

5

REGCAPA

AO

Analog LDO Regulator Output. Decouple this pin to AVSS using a 1 µF and a 0.1 µF capacitor.

6

AVSS

P

Negative Analog Supply. This supply ranges from −2.75 V to 0 V and is nominally set to 0 V.

7

AVDD1

P

Analog Supply Voltage 1. This voltage is 3.3 V or 5 V ± 10% with respect to AVSS.

8

AVDD2

P

Analog Supply Voltage 2. This voltage ranges from 2 V to 5.5 V with respect to AVSS.

9

XTAL1

AI

Input 1 for Crystal.

10

XTAL2/CLKIO

AI/

DI/O

Input 2 for Crystal/Clock Input or Output. Based on the CLOCKSEL bits in the ADCMODE register. The

following four options are available for selecting the MCLK source:

Internal oscillator: no output.

Internal oscillator: output to XTAL2/CLKIO. Operates at IOVDD logic level.

External clock: input to XTAL2/CLKIO. Input must be at IOVDD logic level.

External crystal: connected between XTAL1 and XTAL2/CLKIO.

11

DOUT/RDY

DO

Serial Data Output/Data Ready Output. DOUT/RDY is a dual purpose pin. This pin functions as a serial data

output pin to access the output shift register of the ADC. The output shift register can contain data from

any of the on-chip data or control registers. The data-word/control word information is placed on the

DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the

DOUT/RDY output is three-stated. When CS is low, DOUT/RDY operates as a data ready pin, going low

to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes

high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a

processor, indicating that valid data is available.

12

DIN

DI

Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the

control registers in the ADC, with the register address (RA) bits of the communications register

identifying the appropriate register. Data is clocked in on the rising edge of SCLK.

13

SCLK

DI

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a

Schmitt triggered input, making the interface suitable for opto-isolated applications.

14

CS

DI

Chip Select Input. This is an active low logic input selects the ADC. CS can select the ADC in systems

with more than one device on the serial bus. CS can be hardwired low, allowing the ADC to operate in 3-

wire mode with the SCLK, DIN, and DOUT pins interfacing with the device. When CS is high, the

DOUT/RDY output is three-stated.

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