Electronic Components Datasheet Search |
|
AD5592RBRUZ Datasheet(PDF) 8 Page - Analog Devices |
|
AD5592RBRUZ Datasheet(HTML) 8 Page - Analog Devices |
8 / 42 page AD5592R Data Sheet Rev. C | Page 8 of 42 Table 4. AD5592R-1 Timing Characteristics Parameter 1.8 V ≤ VLOGIC < 3 V 3 V ≤ VLOGIC ≤ 5.5 V Unit Test Conditions/Comments t1 33 20 ns min SCLK cycle time, write operation 50 50 ns min SCLK cycle time, read operation t2 16 10 ns min SCLK high time t3 16 10 ns min SCLK low time t4 15 10 ns min SYNC to SCLK falling edge setup time 2 2 µs max SYNC to SCLK falling edge setup time t5 7 7 ns min Data setup time t6 5 5 ns min Data hold time t7 15 10 ns min SCLK falling edge to SYNC rising edge t8 30 30 ns min Minimum SYNC high time for write operations 60 60 ns min Minimum SYNC high time for register read operations t9 0 0 ns min SYNC rising edge to next SCLK falling edge t10 40 25 ns max SCLK rising edge to SDO valid Figure 3. Load Circuit for Logic Output (SDO) Timing Specifications Figure 4. Timing Diagram 200µA IOL 200µA IOH 1.6V TO OUTPUT PIN CL 25pF SCLK SDI DB15 DB0 t1 t2 t8 t3 t4 t5 t6 t10 t7 t9 SYNC SDO DB15 DB0 |
Similar Part No. - AD5592RBRUZ |
|
Similar Description - AD5592RBRUZ |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |