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AD5671R Datasheet(PDF) 26 Page - Analog Devices |
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AD5671R Datasheet(HTML) 26 Page - Analog Devices |
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26 / 32 page  AD5671R/AD5675R Data Sheet Rev. B | Page 26 of 32 POWER-DOWN OPERATION The AD5671R/AD5675R contain two separate power-down modes. Command 0100 is designated for the power-down function (see Table 9). These power-down modes are software programmable by setting 16 bits, Bit DB15 to Bit DB0, in the input shift register. There are two bits associated with each DAC channel. Table 12 shows how the state of the two bits corresponds to the mode of operation of the device. Any or all DACs (DAC 0 to DAC 7) power down to the selected mode by setting the corresponding bits. See Table 13 for the contents of the input shift register during the power-down/ power-up operation. Table 12. Modes of Operation Operating Mode PD1 PD0 Normal Operation 0 0 Power-Down Modes 1 kΩ to GND 0 1 Tristate 1 1 When both Bit PD1 and Bit PD0 in the input shift register are set to 0, the device works normally with its normal power consumption of typically 1 mA at 5 V. However, for the two power-down modes, the supply current falls to typically 1 µA. In addition to this fall, the output stage switches internally from the amplifier output to a resistor network of known values. This has the advantage that the output impedance of the devices are known while the devices are in power-down mode. There are two different power-down options. The output is connected internally to GND through either a 1 kΩ resistor, or it is left open-circuited (tristate). The output stage is shown in Figure 62. Figure 62. Output Stage During Power-Down The bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when power-down mode is activated. However, the contents of the DAC registers are unaffected in power-down mode, and the DAC registers can be updated while the device is in power-down mode. The time required to exit power-down is typically 2.5 µs for VDD = 5 V. LOAD DAC (HARDWARE LDAC PIN) The AD5671R/AD5675R DACs have double buffered interfaces consisting of two banks of registers: input registers and DAC registers. The user can write to any combination of the input registers. Updates to the DAC registers are controlled by the LDAC pin. Instantaneous DAC Updating (LDAC Held Low) For instantaneous updating of the DACs, LDAC is held low while data is clocked into the input register using Command 0001. Both the addressed input register and the DAC register are updated on the 24th clock, and the output changes immediately. Deferred DAC Updating (LDAC is Pulsed Low) For deferred updating of the DACs, LDAC is held high while data is clocked into the input register using Command 0001. All DAC outputs are asynchronously updated by pulling LDAC low after the 24th clock. The update occurs on the falling edge of LDAC. Figure 63. Simplified Diagram of Input Loading Circuitry for a Single DAC Table 13. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation [DB23:DB20] DB19 [DB18:DB16] DAC 7 DAC 6 DAC 5 DAC 4 DAC 3 DAC 2 DAC 1 DAC 0 [DB15: B14] [DB13: B12] [DB11: B10] [DB9:DB8] [DB7:DB6] [DB5:DB4] [DB3:DB2] [DB1:DB0] 0100 0 XXX1 [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0] 1 X means don’t care. RESISTOR NETWORK VOUT DAC POWER-DOWN CIRCUITRY AMPLIFIER SCL DAC REGISTER INTERFACE LOGIC AMPLIFIER LDAC INPUT REGISTER SDA 12-/16-BIT DAC VOUTX VREF |
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