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AD5671R Datasheet(PDF) 25 Page - Analog Devices

Part No. AD5671R
Description  Base station power amplifiers
Download  32 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD5671R Datasheet(HTML) 25 Page - Analog Devices

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Data Sheet
AD5671R/AD5675R
Rev. B | Page 25 of 32
READ OPERATION
When reading data back from the AD5671R/AD5675R, begin
with a start command followed by an address byte (R/W = 0),
after which the DAC acknowledges that it is prepared to receive
data by pulling SDA low. The address byte must be followed by
the command byte, which determines both the read command
that is to follow and the pointer address to read from; the
command byte is also acknowledged by the DAC. The user
configures the channel to read back the contents of one or more
DAC input registers and sets the read back command to active
using the command byte.
Then, the master establishes a repeated start condition, and the
address is resent with R/W = 1. This byte is acknowledged by the
DAC, indicating that it is prepared to transmit data. Two bytes
of data are then read from the DAC, as shown in Figure 61. A
NACK condition from the master, followed by a stop condition,
completes the read sequence. If more than one DAC is selected,
DAC 0 is read back by default.
MULTIPLE DAC READBACK SEQUENCE
When reading data back from multiple AD5671R/AD5675R
DACs, the user begins with an address byte (R/W = 0), after
which the DAC acknowledges that it is prepared to receive data
by pulling SDA low. The address byte must be followed by the
command byte, which is also acknowledged by the DAC. The
user selects the first channel to read back using the command
byte.
Following this sequence, the master establishes a repeated start
condition, and the address is resent with R/W = 1. This byte is
acknowledged by the DAC, indicating that it is prepared to
transmit data. The first two bytes of data are then read from
DAC Input Register n (selected using the command byte), MSB
first, as shown in Figure 61. The next two bytes read back are the
contents of DAC Input Register n + 1, and the next bytes read
back are the contents of DAC Input Register n + 2. Data is read
from the DAC input registers in this autoincremented fashion
until a NACK followed by a stop condition follows. If the contents
of DAC Input Register 7 are read out, the next two bytes of data
read are the contents of DAC Input Register 0.
Figure 61. I2C Read Operation
FRAME 2
COMMAND BYTE
FRAME 1
SLAVE ADDRESS
1
1
0
0
0
1
A1
A0
R/W
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
9
9
1
START BY
MASTER
ACK BY
AD5671R/AD5675R
ACK BY
AD5671R/AD5675R
SCL
SCL
SDA
1
9
9
1
1
9
9
1
ACK BY
AD5671R/AD5675R
REPEATED START BY
MASTER
ACK BY
MASTER
FRAME 4
MOST SIGNIFICANT
DATA BYTE n
FRAME 3
SLAVE ADDRESS
ACK BY
MASTER
NACK BY
MASTER
STOP BY
MASTER
FRAME 6
MOST SIGNIFICANT
DATA BYTE n + 1
FRAME 5
LEAST SIGNIFICANT
DATA BYTE n
1
0
0
0
1
A1
A0
R/W
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
SDA
SCL
(CONTINUED)
SDA
(CONTINUED)
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB15
DB14 DB13 DB12
DB11
DB10
DB9
DB8


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