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AD5671R Datasheet(PDF) 10 Page - Analog Devices

Part No. AD5671R
Description  Base station power amplifiers
Download  32 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD5671R Datasheet(HTML) 10 Page - Analog Devices

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AD5671R/AD5675R
Data Sheet
Rev. B | Page 10 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. TSSOP Pin Configuration
Figure 5. LFCSP Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
TSSOP
LFCSP
1
19
VOUT1
Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.
2
20
VOUT0
Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.
N/A1
0
EPAD
Exposed Pad. The exposed pad must be tied to GND.
3
1
VDD
Power Supply Input. These devices operate from 2.7 V to 5.5 V. Decouple the VDD supply with a 10 μF
capacitor in parallel with a 0.1 μF capacitor to GND.
4
2
VLOGIC
Digital Power Supply. The voltage on this pin ranges from 1.8 V to 5.5 V.
5
3
SCL
Serial Clock Line. In conjunction with the SDA line, this pin clocks data into or out of the 24-bit input shift
register.
6
4
A0
Address Input. Sets the first LSB of the 7-bit slave address.
7
5
A1
Address Input. Sets the second LSB of the 7-bit slave address.
8
GAIN
Span Set Pin. When this pin is tied to GND, all eight DAC outputs have a span from 0 V to VREF. If this pin is
tied to VLOGIC, all eight DACs output a span of 0 V to 2 × VREF.
9
6
VOUT7
Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.
10
7
VOUT6
Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.
11
8
VOUT5
Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.
12
9
VOUT4
Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.
N/A1
10, 16
NIC
No Internal Connection.
13
11
GND
Ground Reference Point for All Circuitry on the Device.
14
RSTSEL
Power-On Reset Pin. Tie this pin to GND to power up all eight DACs to zero scale. Tie this pin to VLOGIC to
power up all eight DACs to midscale.
15
12
LDAC
Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low updates
any or all DAC registers if the input registers have new data, which simultaneously updates all DAC outputs.
This pin can also be tied permanently low.
16
13
SDA
Serial Data Input. In conjunction with the SCL line, this pin clocks data into or out of the 24-bit input shift
register. SDA is a bidirectional, open-drain data line that must be pulled to the supply with an external
pull-up resistor.
17
14
RESET
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are
ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or
midscale, depending on the state of the RSTSEL pin.
18
15
VREFOUT
Reference Output Voltage. When using the internal reference, this is the reference output pin. This pin is
the reference output by default.
19
17
VOUT3
Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.
20
18
VOUT2
Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.
1 N/A means not applicable.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VOUT0
VDD
VLOGIC
A1
A0
SCL
VOUT1
VOUT3
VREFOUT
RESET
RSTSEL
LDAC
SDA
VOUT6
VOUT7
GAIN
VOUT5
VOUT4
GND
VOUT2
TOP VIEW
(Not to Scale)
AD5671R/
AD5675R
14
13
12
1
3
4
RESET
15 VREFOUT
SDA
LDAC
11 GND
VDD
SCL
2
VLOGIC
A0
5
A1
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE TIED TO GND.
AD5671R/AD5675R
TOP VIEW
(Not to Scale)


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