CY27410FLTXI datasheet(8/29 Pages) CYPRESS

Part #	CY27410FLTXI

Description	RMS phase jitter: 1-ps max at 12-kHz to 20-MHz offset

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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Document Number: 001-89074 Rev. *K

Page 8 of 29

CY27410

Crystal Oscillator

The CY27410 supports various low-cost crystals as a reference

oscillator at IN1 (XIN/XOUT) to generate multiple frequencies in

a single chip. The CY27410 supports a crystal with a nominal

load capacitance specification from 8 pF to 12 pF. As shown in

Figure 2 on page 3, the CY27410 integrates all the components,

such as a feedback resistor and tuning capacitor, to oscillate the

clock with a particular crystal for the following specifications.

To enable proper operation, the crystal specification is divided

into three ranges:

■ Low range (FNOM) = 8 to 12 MHz

■ Midrange = 12 to 20 MHz

■ High range = 20 to 48 MHz

The corresponding crystal parameters are listed in Table 2.

Serial Programming Interface Protocol

The CY27410 uses the SDAT and SCLK pins for a 2-wire serial

interface that operates up to 400 Kb/s in Read and Write modes.

It complies with the I2C bus standard. The basic Write protocol is:

Start Bit; 7-bit Device Address; R/W Bit; Slave Clock

Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit

Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in

MA+2; ACK; and more until STOP Bit.

The basic serial format is shown in Figure 19.

Figure 19. Data Transfer Sequence on the Serial Bus

A valid write operation must have a full 8-bit register address

after the device address word from the master, which is followed

by an acknowledge bit from the slave (SDAT = 0/LOW). The next

eight bits must contain the data word intended for storage. After

the data word is received, the slave responds with another

acknowledge bit (SDAT = 0/LOW), and the master must end the

write sequence with a STOP condition (see Figure 20).

Figure 20. Data Frame Architecture (Write)

Table 2. Crystal Specifications

Range

Min

Frequency

(MHz)

Max

Frequency

(MHz)

Max R1

(ohms)

Max DL

(uW)

Low

8

12

150

100

Mid

12

20

70

100

High

20

48

50

100

CL (pF) for all Ranges

Associated Max C0

(pF)

8

2

9

2

10

2

12

3

SCLK

SDAT

START

Condition

Address or

Acknowledge

Valid

Data may

be changed

STOP

Condition

Device Address

Memory Address

Memory Data

Device Address

Memory Address

Memory Data

Random Write

Sequential Write

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