ADLD8403ACPZ-RL datasheet(4/11 Pages) AD

Part #	ADLD8403ACPZ-RL

Description	Ultralow Power, Adaptive Linear Power, Dual-Port ADSL/ADSL2 Line Driver

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Data Sheet

ADLD8403

SPECIFICATIONS

VCC = 12.5 V, RL = 100 Ω, GDIFF = 13 (fixed), PD_A = 0, PD_B = 0, T = 25°C, typical DSL application circuit, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

−3 dB Small Signal Bandwidth

8

MHz

VOUT = 0.1 V p-p, differential

−3 dB Large Signal Bandwidth

8

MHz

VOUT = 2 V p-p, differential

Differential Gain

12.8

13

13.2

V/V

NOISE/DISTORTION PERFORMANCE

Multitone Power Ratio (MTPR)

−65

dBc

26 kHz to 2.2 MHz, ZLINE = 100 Ω, differential load

Differential Output Noise

120

nV/√Hz

f = 10 kHz

INPUT CHARACTERISTICS

Referred to Output (RTO) Offset Voltage

<100

mV

Single-ended

15

200

mV

Differential

Input Resistance

8

kΩ

Differential

Input Capacitance

1

pF

Differential

OUTPUT CHARACTERISTICS

Differential Output Voltage Swing

43.4

V

ΔVOUT, RL = 100 Ω

POWER SUPPLY

Operating Range, Single Supply

11.75

12.5

V

Total Quiescent Current

Full chip

PD_A = 0, PD_B = 0, PD_PMP = 0

35.6

38

mA

Pumps are on, both channels active

PD_A = 0, PD_B = 0, PD_PMP = 1

22.0

25

mA

Pumps are off, both channels active

PD_A = 0, PD_B = 1, PD_PMP = 0

21.0

23.5

mA

Pumps are on, one channel active

PD_A = 0, PD_B = 1, PD_PMP = 1

10.6

13

mA

Pumps are off, one channel active

PD_A = 1, PD_B = 1

2.5

3.5

mA

Pumps are off, both channels inactive

Common-Mode Voltage

20

mV

With respect to midsupply

Threshold

PD_A = 0, PD_B = 0

0.8

V

PD_A = 1, PD_B = 1

2.4

V

Input Current

PD_A = 0, PD_B = 0

35

60

µA

0 ≡ 0.8 V

PD_A = 1, PD_B = 1

5

10

µA

1 ≡ 2.4 V

Rev. C | Page 3 of 10

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